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Hash algorithm hardware realization device based on FPGA

A hardware implementation and algorithm technology, which is applied in the field of encryption algorithm and large-capacity data search, can solve the problems of impracticality and low Hash performance, and achieve the effect of fast search

Inactive Publication Date: 2016-08-03
ZHEJIANG EBANG COMM
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AI Technical Summary

Problems solved by technology

[0005] At present, Hash algorithms in the industry are basically based on pure software implementation, resulting in low Hash performance, especially in the case of long table entries, high-speed table lookup with large table entries or large data volumes that require encryption, relying on pure software implementation hardly realistic

Method used

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  • Hash algorithm hardware realization device based on FPGA

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Embodiment Construction

[0023] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0024] As shown in the figure, the FPGA-based Hash algorithm hardware implementation device includes a task allocation module, a Hash one-way function module and a result merging module, and the input DATA data is disassembled into n small pieces by the task allocation module, respectively X1, X2...Xn is calculated by n Hash one-way functions in the Hash one-way function module to obtain n KEY values, and then the results are merged and calculated by the result merging module, and finally the KEY value of the DATA data is obtained.

[0025] The working process of the FPGA-based Hash algorithm hardware implementation device of the present invention is as follows, and a comparative test is carried out.

[0026] 1. Make sure the DATA data is 2G in size, and n is 64;

[0027] 2. Select the HASH algorithm of MD5, SHA-1, SHA-256 and SHA-512 as the t...

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Abstract

The invention discloses an FPGA-based Hash algorithm hardware realization device. At present, the HASH algorithm in the industry is basically based on pure software implementation, resulting in low Hash performance, especially in the case of long table entries, high-speed table lookup with large table entries or large data volumes that require encryption, relying on pure software implementation Hardly realistic. The present invention comprises a task distribution module, a Hash one-way function module and a result merging module, and is characterized in that: the input DATA data is disassembled into n small pieces by the task distribution module, which are respectively X1, X2...Xn, and then the Hash single Compute to the n Hash one-way functions in the function module to obtain n KEY values, and then perform the result merging calculation by the result merging module, and finally obtain the KEY value of the DATA data. The invention is mainly based on the FPGA to realize the Hash algorithm, and executes operations concurrently in slices, and the speed is dozens of times faster than that of pure software.

Description

technical field [0001] The invention relates to an encryption algorithm and a large-capacity data search in the field of information security, in particular to an FPGA-based Hash algorithm hardware implementation device. Background technique [0002] With the recent rapid development of the Internet, Internet of Things, cloud computing, and other information technologies, information and data have shown rapid growth. For example, the Alibaba server already has more than 100PB of data (1PB=1024TB). Big data has very broad application prospects in science, finance, meteorology, medical care, environmental protection, education, military, transportation and other fields. Therefore, big data has become an important strategic resource of the country, and how to quickly find useful information in big data has become a hot spot of great concern in academia and industry. [0003] In recent days, as the wide application of Internet finance in the financial field has attracted peopl...

Claims

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Application Information

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IPC IPC(8): H04L9/06
CPCH04L9/0643
Inventor 胡东包兴刚
Owner ZHEJIANG EBANG COMM
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