A sram auxiliary device and working system
A technology for auxiliary devices and working systems, applied in the direction of logic circuits using specific components, logic circuits using basic logic circuit components, digital memory information, etc., can solve the problem of auxiliary circuits, complex structure of DUMMY, occupied area and power consumption major issues
Active Publication Date: 2019-01-11
SHENZHEN PANGO MICROSYST CO LTD
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Problems solved by technology
[0007] The invention provides an auxiliary device and a working system of SRAM, which solves the problem that the existing DUMMY has a complex structure and requires an auxiliary circuit, resulting in a large occupied area and large power consumption
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[0026] The concept of the present invention will be further described in detail through specific embodiments below.
[0027] Such as image 3 As shown, it is a schematic diagram of the auxiliary device of SRAM provided by an embodiment of the present invention. The auxiliary device is different from the existing DUMMY structure. The auxiliary device mainly includes:
[0028] The first unit 31 is configured to output a first output signal according to a first externally connected control signal, and the first output signal is at a high level;
[0029] The second unit 32 is configured to output a second output signal according to a second control signal externally connected, and the second output signal is at a low level;
[0030] One of the first output signal and the second output signal is connected to the bit line BL in a bit line pair more than the SRAM in the data bus, and the other is connected to the bit line BLB in the bit line pair .
[0031] Generally, one auxiliar...
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The invention discloses an auxiliary device and work system for a SRAM. The auxiliary device for the SRAM comprises a first unit, which is used for outputting a first output signal according to a first control signal input from the outside, wherein the first output signal is a high-level signal; and a second unit, which is used for outputting a second output signal according to a second control signal input from the outside, wherein the second output signal is a low-level signal. The number of bit-line pairs in a data bus is one more than the number of bit-line pairs in the SRAM; and one of the first output signal and the second output signal is connected with a bit line BL in the extra one bit-line pair in the data bus while the other is connected with a bit line BLB in the bit-line pair. Thus, the auxiliary device overcomes the problems of a large occupied land area and great power consumption in the prior art caused by a complex dummy structure and need for an auxiliary circuit.
Description
technical field [0001] The present invention relates to the technical field of Static Random Access Memory (SRAM), in particular to an auxiliary device and a working system of SRAM. Background technique [0002] FPGA chips often contain a large number of on-chip SRAMs, which are used as data caches and the like. [0003] Due to the different row and column layouts of the SRAM array, the width of the bit line (Bit Line) may not be consistent with the bit width of the data bus interface in the actual chip. In order to ensure that when data is read from the SRAM array, all data buses can return a definite value instead of an indeterminate state. In existing solutions, DUMMY circuits are usually added to the data buses. Generally, a DUMMY needs to be added for each unused bit line pair of the data bus. For example, for a 6-tube SRAM, a 6-tube SRAM unit needs to be added as a DUMMY. The structure of the 6-tube SRAM is as follows figure 1 As shown, it is also the structure of DU...
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IPC IPC(8): G11C11/413H03K19/177
CPCG11C11/413H03K19/1776
Inventor 夏钊霍杰
Owner SHENZHEN PANGO MICROSYST CO LTD