Manufacturing method for groove grid super junction MOSFET

Abstract

The invention discloses a manufacturing method for a groove grid super junction MOSFET. The manufacturing method comprises the steps of forming a hard mask layer; photoetching the hard mask layer to open a groove forming area; etching for the first time to form a top groove; removing a protection layer at the bottom of the top groove, and reserving the protection layer on the side surface of the top groove; etching for the second time to form a bottom groove; filling the bottom groove with a P-type epitaxial layer to form a bottom epitaxial filled layer; filling the top of the bottom epitaxial filled layer with a P-type epitaxial layer to form a top epitaxial filled layer; removing the hard mask layer and the protection layer and thus forming a grid groove at the periphery of the top of a P-shaped column; and forming a grid dielectric layer in the grid groove and filling a grid conductive material in the grid groove. According to the manufacturing method, the registration deviation between the groove grid and the P-type column can be avoided, the technological stability can be improved and thereby the threshold voltage and breakover voltage drop of the device are more uniform, the size of the super junction unit can be smaller, and the capability of resisting unclamped inductive switching impact can be greatly enhanced.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate superjunction (superjunction) power device. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET can greatly reduce the on-resistance of the device by using a...

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Problems solved by technology

[0013] figure 2 Although the trench gate structure shown can reduce the size of the device, in the actual process, whether the P-type pillar 3 is formed by multi-layer epitaxy or epitaxial filling, because the P-type pillar 3 and the trench gate, that is, the polysilicon gate 6, are two Sub-photolithography formation, the registration deviation in the process will lead to the situation that the P-type pillar 3 affects the accumulation area of ​​the trench gate; the accumulation area of ​​the trench gate is located at the bottom of the P-type body region 5 and is covered by the side of the polysilicon gate 6 When there is a misregistration between the N-type epitaxial layer 2, the P-type pillar 3 and the trench gate, the lateral size of the accumulation region will be affected, which will deteriorate the turn-on voltage and turn-on voltage drop of the device

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