Method of manufacturing trench gate super junction power device

Abstract

The invention discloses a method of manufacturing a trench gate super junction power device. The method comprises steps: a hard mask layer is formed on the surface of an N-type epitaxial layer; a photoetching process is adopted to simultaneously define a first trench forming area and a second trench forming area of the trench gate and the super junction; first-time etching is carried out on the epitaxial layer until reaching the depth required by the first trench; a protective layer is formed to cover the inner-side surface of the first trench; second-time etching is carried out on the N-type epitaxial layer, wherein the second-time etching only etches the N-type epitaxial layer in the second trench forming area until reaching the depth required by the second trench; epitaxial filling of P-type silicon is carried out in the second trench; and the hard mask layer and the protective layer are removed and a gate dielectric layer is formed in the first trench and a gate conductive material is filled. Registration deviation between the trench gate and a P-type column can be prevented, the process stability can be improved, turn-on voltage and forward voltage drop of the device can be more uniform, and the size of the super junction unit can be smaller.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate superjunction (superjunction) power device. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET can greatly reduce the on-resistance of the device by using a...

AI Technical Summary

Problems solved by technology

[0013] figure 2 Although the trench gate structure shown can reduce the size of the device, in the actual process, whether the P-type column 3 is formed by multi-layer epitaxy or epitaxial filling, because the P-type column 3 and the trench gate, that is, the polysilicon gate 6, are two Sub-lithography formation, registration deviation in the process will lead to the situation that the P-type pillar 3 affects the accumulation area of ​​the trench gate; the accumulation area of ​​the trench gate is located at the bottom of the P-type body region 5 and is covered by the side of the polysilicon gate 6 When there is a misregistration between the N-type epitaxial layer 2, the P-type pillar 3 and the trench gate, the lateral size of the accumulation region will be affected, which will deteriorate the turn-on voltage and turn-on voltage drop of the device

Images