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A package structure for optoelectronic integrated chip

A packaging structure and integrated chip technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve problems affecting the transmission and reflection characteristics of devices, and achieve the effects of reducing the impact, avoiding the use of gold wires, and good impedance matching

Active Publication Date: 2018-10-09
山东中科际联光电集成技术研究院有限公司
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AI Technical Summary

Problems solved by technology

This method causes parasitic inductance and parasitic capacitance between the gold wires and between the gold wire and the pad, which seriously affects the transmission and reflection characteristics of the device under high frequency conditions

Method used

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  • A package structure for optoelectronic integrated chip
  • A package structure for optoelectronic integrated chip
  • A package structure for optoelectronic integrated chip

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Embodiment Construction

[0026] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0027] The invention discloses a packaging structure for an optoelectronic integrated chip, comprising:

[0028] A dielectric substrate, which mainly plays the role of supporting the surface electrodes and confining the electromagnetic field; the surface of the dielectric substrate is evaporated with a certain thickness of coplanar waveguide electrodes by thin film technology, that is, the ground electrode G, the signal electrode S, and the thin film resistance;

[0029] A metal via post, mainly used for signal transmission, connecting signal electrodes and chip electrodes, and supporting dielectric substrate; it can be made by via hole and filling process;

[0030] A matching resistor, connected in parallel with the chip...

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Abstract

The invention relates to a packaging structure for a photoelectron integrated chip. The packaging structure comprises a dielectric substrate, a metallic conduction post, and a matched resistor. A ground electrode G, a signal electrode S, a matched resistor for impedance matching are arranged on the surface of the dielectric substrate, wherein the ground electrode G and the signal electrode S are used for external and electric connection. The metallic conduction post is used for connecting the signal electrode and an electrode of a photoelectron integrated chip, thereby realizing signal transmission between the signal electrode and the electrode of the photoelectron integrated chip; and the matched resistor connected in series between the signal electrode S and the ground electrode G is connected in parallel with the photoelectron integrated chip to realize non-gold-wire impedance matching, thereby realizing impedance matching of a high-internal-resistance chip. According to the packaging structure, gold wire usage is avoided completely; and the influence on the device performance by a parasitic parameter introduced by the gold wire can be reduced. The packaging structure is suitable for packaging of single-channel or multi-channel integrated chips.

Description

technical field [0001] The invention belongs to the field of optoelectronic / microelectronic devices, and more specifically relates to a packaging structure for optoelectronic integrated chips. Background technique [0002] In the packaging of optoelectronic chips, due to the high resistance characteristics of electro-absorption modulators or other devices, there will be impedance mismatch with the existing 50Ω communication system, which will seriously affect the final performance of the chip. Usually, in order to achieve impedance matching, a 50Ω resistor needs to be connected in parallel to the high-resistance device, which is the most common method in the packaging of high-speed optoelectronic integrated chips. However, when connecting matching resistors in parallel, it is necessary to use a large number of gold wires (especially in multi-channel array integrated chip packages) to respectively connect the transmission line and the electrodes of the high-resistance device,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/64
CPCH01L23/647
Inventor 张志珂刘宇赵泽平刘建国祝宁华
Owner 山东中科际联光电集成技术研究院有限公司
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