Array substrate, manufacturing method thereof, and display device

Abstract

The invention provides an array substrate and a manufacture method thereof and a display device, and belongs to the technical field of display. The manufacture method comprises the following steps: forming an isolation pad pattern at a preset position on a substrate base plate; forming a first conductive pattern on the isolation pad pattern; forming an insulating layer comprising a via hole on the substrate base plate, where the first conductive pattern is formed; and forming a second conductive pattern on the insulating layer, wherein the first conductive pattern is connected with the second conductive pattern through the via hole running through the insulating layer; orthographic projection of the via hole on the substrate base plate and orthographic projection of the isolation pad pattern on the substrate base plate are at least partially overlapped. The technical scheme can prevent the defect of Mura, and improves display effect of the display device.

Description

Technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] In the prior art, the pixel electrode on the array substrate and the drain electrode of the thin film transistor are located in different layers, the pixel electrode and the drain electrode of the thin film transistor are covered with a passivation layer, and a conductive connection line is formed on the passivation layer. The pixel electrode and the drain electrode of the thin-film transistor are connected through the via hole penetrating the passivation layer. Because the thickness of the passivation layer is relatively large, the depth of the via hole is also relatively large, and the deep hole is prone to dents, resulting in an array substrate When the alignment film is coated, the alignment film is prone to spread unevenly at the deep holes, resulting in the problem of...

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Problems solved by technology

[0002] In the prior art, the pixel electrode on the array substrate and the drain electrode of the thin film transistor are located in different layers, and the pixel electrode and the drain electrode of the thin film transistor are covered with a passivation layer, and a conductive connection line is formed on the passivation layer, and the conductive connection line The pixel electrode and the drain electrode of the thin film transistor are connected through a via hole penetrating the passivation layer. Since the thickness of the passivation layer is relatively large, the depth of the via hole is also relatively large. Since depressions are prone to appear in the deep hole, resulting in the When coating the alignment film, the alignment film is prone to uneven diffusion in the deep holes, which leads to the problem of display Mura (unevenness) in the final display product

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