Semiconductor device and design device

A technology of semiconductors and computing processing devices, which is applied in the direction of measuring devices, CAD circuit design, computer-aided design, etc., and can solve problems affecting test costs and other issues

Active Publication Date: 2020-07-03
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Circuits with many stages of scan chains require a long time to scan test, thereby greatly affecting the cost of test

Method used

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  • Semiconductor device and design device
  • Semiconductor device and design device
  • Semiconductor device and design device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0040] The following should refer to figure 1 A semiconductor device according to the first embodiment is explained. figure 1 is a schematic diagram showing the configuration of the semiconductor device 1 according to the first embodiment. Such as figure 1As shown, a semiconductor device 1 includes a plurality of MMSFFs (Multimode Support Scan Flip Flops) 10 , a multimode control circuit 20 , and a compressor 30 . In this example, scan chain configurations with different numbers of scan chains shall be called modes individually, and multiple modes shall be called multi-mode. The multi-mode support scan flip-flop is a flip-flop that can have multiple scan chain configurations, and the multiple scan chain configurations have different compression ratios by selecting and outputting external input test signals or shift test signals.

[0041] In the semiconductor device 1, one or more MMSFFs 10 are connected in series to thereby establish one or more scan chains. The expande...

no. 2 example

[0073] The following should refer to Figure 5 A semiconductor device according to the second embodiment is explained. Figure 5 is a schematic diagram showing the configuration of a semiconductor device 1A according to the second embodiment. Such as Figure 5 As shown, a semiconductor device 1A includes a plurality of MMSFFs 10, a multimode control circuit 20, and a variable compression ratio compressor 30A. The difference between the first embodiment and the second embodiment is that in the second embodiment, instead of the compressor 30 included in the first embodiment, a variable compressor 30A is included.

[0074] The variable compressor 30A can change the compression ratio according to the number of scan chains. The variable compressor 30A includes an XOR (exclusive OR) tree and a MUX (multiplexer) 31 (31a to 31c). The output from each MMSFF 10 is input to the XOR gates that make up the XOR tree. For example, if Figure 5 As shown, the output from the first and fi...

no. 3 example

[0080] The following should refer to Figure 6 A semiconductor device according to the third embodiment is explained. Figure 6 is a schematic diagram showing the configuration of the semiconductor device 1B according to the third embodiment. Such as Figure 6 As shown, the semiconductor device 1B includes a plurality of MMSFFs 10 , a multimode control circuit 20 , a variable compression ratio compressor 30B, and a mask control circuit 40 . The second embodiment differs from the third embodiment in that in the third embodiment, a variable compressor 30B is included instead of the variable compressor 30A included in the second embodiment, and a variable compressor 30B for controlling Masking control circuit 40 of transcompressor 30B.

[0081] In a similar manner to variable compressor 30A, variable compressor 30B includes MUX 31 (31a to 31c). Further, in the first stage, masking circuits 32 are respectively provided to the input sides of the four XOR gates. More specifical...

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PUM

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Abstract

Various embodiments of the present invention relate to semiconductor devices and design devices. In compressive scanning, the number of test steps is reduced without reducing detection efficiency. The semiconductor device includes: one or more scan chains, wherein each scan chain includes one or more MMSFFs connected in series; and a combinational circuit; and the semiconductor device is switchable between a scan shift operation and a capture operation. The MMSFF includes: a MUX that selects one of an external input test signal input externally and a shift test signal input via the MMSFF in a preceding stage in the same scan chain; and a FF that outputs the external input test signal and the shift test signal One of the bit test signals that has been selected by the MUX.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2015-054607 filed on March 18, 2015, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to a semiconductor device and a design device, and to, for example, a semiconductor device capable of performing a variable compression scan test and a design device for the semiconductor device. Background technique [0004] A common method of testing LSI (Large Scale Integration) is scan testing. In the scan test, the FFs in the circuit are replaced by FFs called scan flip-flops (FFs) having a multiplexer (MUX). The MUX toggles between a test input and a normal operating input by scanning the enable signal. [0005] At the time of the scan test, the scan FFs are connected to each other in series so that the scan FFs operate as shift registers that c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851G01R31/318563G01R31/318566G06F30/30
Inventor 岩田浩幸
Owner RENESAS ELECTRONICS CORP
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