Chip packaging structure and manufacture method thereof

Abstract

The invention provides a chip packaging structure and a manufacture method thereof. The chip packaging structure includes a substrate, at least one chip, a plurality of conductive bumps, and an insulating thermally conductive material. The chip is disposed on a chip carrier, and the chip carrier is disposed on the substrate. The conductive bumps are disposed between the substrate and the chip carrier to electrically connect the substrate with the chip. The insulating thermally-conductive material is disposed between the conductive bumps and covers the conductive bumps.

Description

technical field [0001] The invention relates to a chip packaging technology, and in particular to a chip packaging structure with insulating and heat-conducting materials and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) is mainly divided into three stages: wafer (Wafer) manufacturing, integrated circuit fabrication, and integrated circuit packaging (Package). Chips are completed through steps such as wafer fabrication, circuit design, photomask fabrication, and wafer dicing. Each chip formed by dicing the wafer can be covered with a sealing material after being electrically connected to external signals through the contacts on the chip. The purpose of its packaging is to prevent the chip from being affected by moisture, heat, and noise, and to provide a medium for electrical connection between the chip and the external circuit, thus completing the packaging step o...

AI Technical Summary

Problems solved by technology

However, the external heat sink will take up a lot of volume, thus creating design constraints for the overall electronics enclosure

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