Transactional memory support

Abstract

An asymmetric multiprocessor system (2) includes multiple processor cores (4, 6) supporting transactional memory via controllers (14, 16) and one or more processor cores (8) not supporting transactional memory via hardware ). The controller responds to receipt of a request for exclusive access to a lock address by determining whether their associated processing elements are currently executing a memory transaction protected by the lock value stored at the lock address, and if their processing If the element is executing such a transaction, release of the lock address for exclusive access is delayed until a predetermined condition is met. If the processing element is not executing such a protected memory transaction, the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and / or that the request has previously been received and rejected a threshold number of times. The request may be generated by execution of a transaction start instruction to read the lock address from the architectural register (76) storing the lock address (if the processor executing the transaction start instruction is not executing an ongoing memory transaction). If the processor is already executing a memory transaction, the transaction start instruction does not need to access the lock value stored at the lock address held in the lock address register (76), because the lock value is assumed to have already been checked.

Description

technical field [0001] This disclosure relates to the field of data processing systems. More specifically, the present disclosure relates to support for transactional memory within a data processing system having multiple processing elements that store shared data values ​​within memory. Background technique [0002] It is known to provide data processing systems with multiple processing elements sharing data values ​​stored in memory. To control coherency among processing elements, it is known to provide locks associated with regions of memory address space such that when a processing element wishes to perform an access to that region, it first checks the Lock value is not set. If the lock value is set, this indicates that another processing element is already executing a transaction within the region, so the current access should be aborted and retried at a later time. If the test reveals that the lock is not currently set, the processing element that made the access re...

AI Technical Summary

Problems solved by technology

[0003] Although the use of locks provides a safe mechanism for sharing data values ​​between processing elements, it can adversely affect performance because locks may be set at a coarse-grained level such that they do not actually affect the same data values ​​within the locked region. Memory accesses are prevented from running in parallel when in practice they can be done in parallel without difficulty

Disadvantageously, if locks are set at too fine a granularity, the level of overhead associated with storing and managing locks becomes onerous

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