LDMOS transistor and formation method thereof
A transistor and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of poor performance of fin-type LDMOS transistors, and achieve the effect of increasing the step-down distance and improving the withstand voltage.
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Embodiment 1
[0076] This embodiment is described by taking a case where two adjacent LDMOS transistors share a common drain.
[0077] combined reference Figure 9 and Figure 10 , providing a semiconductor substrate 20 having a first fin 211 , a second fin 212 and a third fin 213 , and a first fin between the first fin 211 and the second fin 212 The isolation structure 221 , the second isolation structure 222 located between the second fin 212 and the third fin 213 .
[0078] In this embodiment, the semiconductor substrate 20 is a silicon substrate, and the semiconductor substrate 20 has a first well region opposite to the type of the subsequently formed transistor in the semiconductor substrate 20, and has a second well region of the same type as the subsequently formed transistor in the first well region. well region 215 . There are a first isolation structure 221 and a second isolation structure 222 in the second well region 215 . Moreover, the first isolation structure 221 and the ...
Embodiment 2
[0164] refer to Figure 16 , the present invention also provides an LDMOS transistor structure, two adjacent LDMOS transistors share one drain. Specifically include:
[0165] A semiconductor substrate 20 having a first fin 211 , a second fin 212 and a third fin 213 . The semiconductor substrate 20 further has a first isolation structure 221 located between the first fin 211 and the second fin 212, and a second isolation structure 222 located between the second fin 212 and the third fin 213;
[0166] a first gate structure 231 across the first fin 211 , the first gate structure 231 covering the top and sidewalls of the first fin 211 ;
[0167] a second gate structure 232 across the third fin 213, the second gate structure 232 covering the top and sidewalls of the third fin 213;
[0168] the first source 241 located in the first fin portion 211 on the side of the first gate structure 231 away from the first isolation structure 221;
[0169] forming a second source 243 in the...
Embodiment 3
[0193] refer to Figure 17 This embodiment provides a method for forming an LDMOS transistor. The difference between this embodiment and Embodiment 1 is that Embodiment 1 has two sources, namely a first source and a second source. The first source and the second source share one drain. The LDMOS transistor in this embodiment has only one source 341 , and the drain 342 is not a common drain. That is to say, in this embodiment, there is no third fin and the second shallow trench isolation structure. Specifically include:
[0194] providing a semiconductor substrate 30, the semiconductor substrate has a first fin 311, a second fin 312 and a first isolation structure 321 between the first fin 311 and the second fin 312;
[0195] forming a gate structure 331 across the first fin portion 311, the gate structure 331 covering the top and sidewalls of the first fin portion 311, the first gate structure covering part of the first isolation structure;
[0196] forming a source 341 in...
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