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Translation lookaside buffer

A buffer and back-up technology for instrumentation, memory systems, climate sustainability, etc., to address performance degradation, inefficient use of resources, etc.

Inactive Publication Date: 2016-11-30
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the use of multithreading and / or virtualization often results in inefficient use of resources such as caches or TLBs, which can then become bottlenecks degrading performance

Method used

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  • Translation lookaside buffer
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  • Translation lookaside buffer

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Embodiment Construction

[0016] The detailed description, set forth below in conjunction with the accompanying drawings, is intended as a description of some exemplary, non-limiting embodiments and various other embodiments may be practiced and contemplated, as will be apparent to those skilled in the art. The described embodiments are provided as examples or illustrations of the present disclosure only. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these specific details. In some instances, well-known structures and devices are not shown in block diagram form in order to avoid obscuring the concepts of the present disclosure. Acronyms and other descriptive terms may be used merely for convenience and clarity and are not intended to limit the scope of the disclosure. In general, the disclosed ...

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PUM

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Abstract

Translation lookaside buffer (TLB). Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support virtualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

Description

technical field [0001] The subject matter disclosed herein relates generally to processors, and more specifically to memory management using translation lookaside buffers. Background technique [0002] A memory management unit (MMU) on a computer system can map the virtual address space to the physical address space. A virtual address space represents the set of logical or virtual addresses available to a process. For example, a virtual address space may be divided into pages, and a virtual address may be represented by a virtual page number (eg, some most significant bits of the virtual address) and an offset within the page (eg, the remaining least significant bits of the virtual address). The MMU can maintain page tables that associate virtual page numbers with physical page numbers. By looking up the page table entry using the virtual page number as an index, the MMU can obtain the corresponding physical page number, which can be combined with the offset to obtain the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/1027
CPCG06F12/1027G06F12/0844G06F12/1054Y02D10/00G06F12/1009G06F2212/652G06F2212/684
Inventor R·J·罗扎里奥S·帕特尔
Owner MIPS TECH INC