A High Speed ​​Sense Amplifier

Abstract

The invention discloses a high-speed induction amplifier. The high-speed induction amplifier comprises a reference current module, a storage unit and a comparator. The high-speed induction amplifier further comprises a pre-charging circuit used for pre-charging a voltage of a bit line (BL) to a reference voltage at the beginning of readout, a column decoder used for finishing column decoding of a selected unit, a reference voltage generation circuit used for generating a reference voltage required by the comparator during readout, a reference clamping protection circuit used for limiting voltages of two input ends of the comparator in the pre-charging and readout processes, and an equipotential circuit used for controlling the voltages of the two input ends of the comparator to be equal or controlling a voltage difference to be as small as possible when the pre-charging is finished. According to the high-speed induction amplifier, the voltage of the bit line is pre-charged to a 1.2V voltage by directly using the pre-charging circuit powered by a 1.2V power supply, and a conventional bit line clamping circuit is replaced, so that the voltage of the bit line is increased, an induction window is expanded, an induction delay is shortened, the voltage settling time of the bit line is avoided, and the reading speed of the induction amplifier is increased.

Description

technical field [0001] The invention relates to a high-speed inductive amplifier, in particular to a high-speed inductive amplifier suitable for flash memory. Background technique [0002] Currently, reading information from floating gate memory cells is usually done using figure 1 The sense amplifier (sense amplifier) ​​structure shown includes a reference current generator 101, a precharge circuit 102, a reference voltage generator 103, a bit line clamping circuit 104, a column decoder 105, etc., figure 2 yes figure 1 An implementation of the structure, I REF Is the reference current, usually by the current mirror with the reference cell current (the reference current generator is usually based on the reference cell (reference cell, other cells the same as the storage unit) to generate a reference current, called a certain proportion of the reference cell current (reference cell current) ( Typically obtained by mirroring 30% of the reference cell current, I CELL is th...

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Problems solved by technology

[0004] The clamping circuits in (1), (a) and (b) include feedback loops, and the pre-charging process needs a stable time. Transistor gate-source voltage V GS (i.e. clamping transistor gate voltage V BIAS and source voltage V S difference, corresponding to figure 2 VC1 and VD1) decrease, the pre-charge speed slows down, and the pre-charge time is longer

[0005] (2), the bit line voltage is usually clamped at 0.5 ~ 0.8V, resulting in a small current difference (cell current gap, that is, I CELL -I REF ), requiring a longer sensing time

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