Layout design method of sampling MOM capacitors in pipeline analog-digital converter (ADC) system

Abstract

The present invention discloses a layout design method of sampling MOM capacitors in a pipeline analog-digital converter (ADC) system. The method comprises the steps of determining a height of an MOM sampling array according to heights of an upper-level amplifier and a lower-level sampling switch; determining a height of an MOM capacitor according to the height of the MOM sampling array; selecting a number of metal layers of the MOM capacitor; setting a capacitance of the MOM capacitor, and selecting a capacitance parameter of the MOM capacitor; and determining metal trends of an input end and an output end of the MOM capacitor according to positions of the upper-level amplifier and the lower-level sampling switch. According to the disclosed methods determining the capacitance parameter, the capacitor height, and the metal trends of the input end and the output end of the MOM capacitor, the mismatch rate of the MOM capacitors within the range of process error gradient is the lowest, therefore, parasitic capacitances between an ADC sampling data input end and a capacitor public end are equal.

Description

technical field [0001] The invention relates to the technical field of layout design of MOM capacitors, in particular to a layout design method for sampling MOM capacitors in a pipeline ADC system. Background technique [0002] As people have higher and higher requirements for the speed and precision of the analog-to-digital converter (ADC), due to the consideration of low power consumption and low cost, the continuous reduction of device size and the continuous reduction of power supply voltage have made high-speed and high-speed Sampling MOM capacitor layout matching for precision ADCs is becoming increasingly challenging. Among various types of ADCs, the ADC with a pipeline structure (pipeline) coordinates the contradiction between area and speed well, but when realizing a high-resolution pipeline ADC, errors caused by device mismatch factors (capacitance Mismatch) is not eliminated, it will have a serious impact on the performance of the ADC. Among all capacitor types (...

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Problems solved by technology

[0004] (1) Random matching error. The random error is determined by the matching characteristics and depends on the size of the unit MOM capacitor. Usually, the size of the capacitor is increased as much as possible to reduce the adverse effects of the random matching error on the circuit, but at the same time it will make the output of the capacitor array The length of the wiring to the pre-amplifier and the post-stage switch is extended, and they do not match each other, and need to be adjusted appropriately according to the area;

[0005] (2) The two-dimensional gradient error, that is, the gradient error in the X direction and the Y direction, has a linear characteristic. In the MOM array, since each unit device is connected by metal, there is resistance and capacitance in the metal line, along the direction of data flow , there is a gradient change in the voltage, and this voltage gradient change will lead to inconsistent data sampling;

[0006] (3) Temperature field error, the chip will dissipate heat when working, so that the temperature on the chip will gradually decrease from a certain point to the surroundings, resulting in inconsistent delays between the sampling data group lines, especially for ADC chips, because large The working current of most chips is very large, with several amperes of current. To reduce this error, it is necessary to distribute the units symmetrically in the center

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