Bidirectional FIFO and bus bridging system

Abstract

The invention provides a bidirectional FIFO (First Input First Out) which comprises a dual port RAM (random access memory), a first set of ports and a second set of ports, wherein the first set of ports comprises a first clock signal input terminal, a first enable signal input terminal, a first read / write control signal input terminal, a first operation address input terminal, a first data input terminal and a first data output terminal; the second set of ports comprises a second clock signal input terminal, a second enable signal input terminal, a second read / write control signal input terminal, a second operation address input terminal, a second data input terminal and a second data output terminal; input signals of the first enable signal input terminal, the first read / write control signal input terminal, the second enable signal input terminal and the second read / write control signal input terminal are combined logic output signals of external read / write signals. Compared with the prior art, the bidirectional FIFO provided by the invention can reduce the hardware cost of an FIFO part to almost half of the original cost, and increases the use efficiency from 50% to 100%.

Description

technical field [0001] The invention relates to the communication field, in particular to an asynchronous two-way FIFO and bus bridge system for communication. Background technique [0002] FIFO (First Input First Out, first-in-first-out array) is a technology widely used in communication systems, which can cache data that is too late to process temporarily. In addition to the data line, the FIFO has control signals such as write and full at the input, and control signals such as read and empty at the output. The FIFO can also perform error communication between two different clock domains. When the read and write clock frequencies and phases on both sides of the FIFO are the same, the FIFO is called a synchronous FIFO, otherwise it is an asynchronous FIFO. [0003] Due to the same clock domain of the synchronous FIFO, the information of the read and write parties can be directly transmitted to each other, and the synchronous FIFO can be very conveniently controlled accordi...

AI Technical Summary

Problems solved by technology

This one-way FIFO consumes a lot of hardware resources

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