Latch and frequency divider
A latch and transistor technology, applied in pulse technology, logic circuits, electrical components, etc., can solve the problem of high circuit power consumption, and achieve the effect of reducing power consumption and reducing power consumption
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[0081] refer to figure 1 , a schematic structural diagram of a high-speed divide-by-two circuit in the prior art is given, including latches 101 and 102 .
[0082] Both the latch 101 and the latch 102 are D flip-flops, the terminals D and Dn are both input terminals, and the terminals Q and Qn are both output terminals. A clock signal CK is input to the clock signal input terminal CLK of the latch 101 , and a clock signal CKb is input to the clock signal input terminal CLK of the latch 102 , and the clock signal CK and the clock signal CKb are inverted.
[0083] The D terminal of the latch 101 is coupled to the Qn terminal of the latch 102, the Q terminal is coupled to the D terminal of the latch 102, the Dn terminal is coupled to the Q terminal of the latch 102, and the Qn terminal is connected to the latch 102. The Dn end of 102 is coupled. That is: the input end of the latch 101 is coupled to the output end of the latch 102 respectively, the output end of the latch 101 is...
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