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Power semiconductor device and manufacturing method thereof

A technology for power semiconductors and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting device performance, etc., and achieve the effect of low contact resistance

Inactive Publication Date: 2017-01-18
GPOWER SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of this, an embodiment of the present invention provides a power semiconductor device and its manufacturing method to solve the technical problem that high temperature affects device performance when RTA process is used to form ohmic contacts in the prior art

Method used

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  • Power semiconductor device and manufacturing method thereof
  • Power semiconductor device and manufacturing method thereof
  • Power semiconductor device and manufacturing method thereof

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Experimental program
Comparison scheme
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Embodiment 1

[0045] Figure 1a and Figure 1b Both are structural schematic diagrams of a power semiconductor device provided in Embodiment 1 of the present invention. Specifically, the power semiconductor device provided in the embodiment of the present invention has a groove structure with peak-shaped sub-grooves formed on the barrier layer. specific, Figure 1a In the power semiconductor device shown, the groove structure stops in the barrier layer, Figure 1b In the power semiconductor device shown, the groove structure terminates in the channel layer. like Figure 1a and Figure 1b As shown, the power semiconductor device may include:

[0046] Substrate 101;

[0047] a channel layer 102 located above the substrate 101;

[0048] a barrier layer 103 located above the channel layer 102;

[0049] The source 104, the gate 105 and the drain 106 above the barrier layer 103, a two-dimensional electron gas 107 is formed at the interface between the channel layer 102 and the barrier layer ...

Embodiment 2

[0085] Figure 3a and Figure 3b A schematic diagram of the structure of a power semiconductor device provided by Embodiment 2 of the present invention. This embodiment is based on the above-mentioned Embodiment 1, and improvements are made on the basis of Embodiment 1. Specifically, the shape of the sub-groove is improved. Specifically, in the power semiconductor device provided by the embodiment of the present invention, a groove structure having vertical sub-grooves is formed on the barrier layer. specific, Figure 3a In the power semiconductor device shown, the groove structure stops in the barrier layer, Figure 3b In the power semiconductor device shown, the groove structure terminates in the channel layer. like Figure 3a and Figure 3b As shown, the power semiconductor device may include:

[0086] Substrate 101;

[0087] a channel layer 102 located above the substrate 101;

[0088] a barrier layer 103 located above the channel layer 102;

[0089] The source 10...

Embodiment 3

[0094] Figure 4a and Figure 4b A schematic diagram of the structure of a power semiconductor device provided by Embodiment 3 of the present invention. This embodiment is based on the above-mentioned Embodiment 1 and Embodiment 2, and is improved on the basis of the above-mentioned embodiment. Specifically, the shape of the sub-groove Make improvements. Specifically, in the power semiconductor device provided by the embodiment of the present invention, a groove structure having trapezoidal sub-grooves is formed on the barrier layer. specific, Figure 4a In the power semiconductor device shown, the groove structure stops in the barrier layer, Figure 4b In the power semiconductor device shown, the groove structure terminates in the channel layer. like Figure 4a and Figure 4b As shown, the power semiconductor device may include:

[0095] Substrate 101;

[0096] a channel layer 102 located above the substrate 101;

[0097] a barrier layer 103 located above the channel...

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Abstract

The invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device includes a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode and a drain electrode; the channel layer is arranged on the substrate; the barrier layer is arranged on the channel layer; the source electrode, the gate electrode and the drain electrode are arranged on the barrier layer; a two-dimensional electron gas is formed at the interface of the channel layer and the barrier layer; the gate electrode is located between the source electrode and the drain electrode; a groove structure corresponding to the source electrode and / or a groove structure corresponding to the drain electrode is formed in the barrier layer; and the bottom of the source electrode and / or the bottom of the drain electrode is located in the corresponding groove structure; and the groove structures are in ohmic contact with the barrier layer and / or the channel layer. With the power semiconductor device provided by the above technical schemes of the invention adopted, the technical problem of influence on device performance caused by high temperature when an RTA process is adopted to form ohmic contact in the prior art can be solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method thereof. Background technique [0002] Gallium nitride (GaN), as a typical representative of wide bandgap semiconductor materials, has the advantages of wider bandgap width, higher saturation electron migration velocity, greater critical breakdown electric field strength and better thermal conductivity. GaN Able to form AlGaN / GaN heterojunction with aluminum gallium nitride (AlGaN). AlGaN / GaN heterojunction devices have great potential in the application fields of radio frequency devices and power electronic devices. How to form a low-resistance ohmic contact on such materials has always been a research hotspot. The performance of the electrode ohmic contact directly affects the output source-leakage current and knee voltage of the device, which in turn affects the RF performance and efficiency of the device. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/41H01L29/423H01L29/778H01L21/336
CPCH01L29/778H01L29/0688H01L29/41H01L29/42312H01L29/66431
Inventor 吴传佳
Owner GPOWER SEMICON
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