Unlock instant, AI-driven research and patent intelligence for your innovation.

Soc-oriented on-chip tddb degradation monitoring and failure warning circuit

A circuit and control circuit technology, applied in the field of on-chip TDDB degradation monitoring and failure early warning circuits, can solve problems such as poor early warning accuracy, false alarms, and inability to monitor performance degradation processes

Active Publication Date: 2019-05-03
FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] (1) Only applicable to hybrid CMOS integrated circuits;
[0007] (2) The comparator output module is also under stress, causing stress TDDB failure breakdown, which may lead to false alarms;
[0008] (3) The output of this circuit only has the alarm function of jumping from "0" to "1" or "1" to "0", and cannot monitor the performance degradation process
[0009] In summary, the TDDB failure early warning circuit has the risk of poor early warning accuracy during use, and cannot monitor the performance degradation process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Soc-oriented on-chip tddb degradation monitoring and failure warning circuit
  • Soc-oriented on-chip tddb degradation monitoring and failure warning circuit
  • Soc-oriented on-chip tddb degradation monitoring and failure warning circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] Embodiments of the SoC-oriented on-chip TDDB degradation monitoring and failure early warning circuit of the present invention will be described below in conjunction with the accompanying drawings.

[0025] refer to figure 2 as shown, figure 2 It is the structural block diagram of the on-chip TDDB degradation monitoring and failure early warning circuit facing SoC of the present invention, including:

[0026] Sequential logic module 100, control circuit module 200, TDDB performance degradation digital conversion module 300, output selection module 400, counter module 500; wherein, the counter module 500 includes counter A and counter B; the TDDB performance degradation digital conversion module 300 Including two sets of identical MOS tube circuits, the first MOS tube circuit and the second MOS tube circuit;

[0027] Described sequential logic module 100 comprises X, Y, CP signal input end and Q1, Q0 output end, under the control of input X signal, Y signal, CP (Cloc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an SoC-oriented on-chip TDDB degradation monitoring and failure early warning circuit. The control circuit module converts Q1 and Q0 signals into switch state control signals and outputs them to the TDDB performance degradation digital conversion module; the first TDDB performance degradation digital conversion module The MOS tube of the MOS tube circuit is in the stress state of the power supply voltage, and the MOS tube of the second MOS tube circuit is in the non-stress state; the first MOS tube circuit and the second MOS tube circuit are under the control of the switch state control signal, respectively output The first frequency value and the second frequency value are sent to the output selection module; the output selection module outputs the first frequency value output by the TDDB performance degradation digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. Record; the counter module determines the degradation amount of TDDB performance by comparing the first frequency value with the second frequency value. The invention has a simple structure, the output can monitor the TDDB performance degradation process, and can accurately warn the TDDB performance.

Description

technical field [0001] The invention relates to the technical field of electronic system monitoring, in particular to an SoC-oriented on-chip TDDB degradation monitoring and failure early warning circuit. Background technique [0002] With the development of complex electronic systems in the direction of miniaturization, high integration, and multi-function, System-on-Chip (SoC) emerges as the times require, and it is more and more widely used in high-reliability technology fields such as aerospace, rail transit, and nuclear power. . However, as the feature size of the device continues to shrink in proportion, the thickness of the gate oxide layer continues to become thinner, and the power supply voltage should not be reduced. The reliability of the gate oxide layer of transistors in SoC under high electric field strength has become a prominent problem. The performance degradation of the gate oxide layer will cause the threshold voltage drift of the device, the decrease of ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/7814G06F2015/763G01R31/14G06F11/076G01R31/2884G06F11/008G01R31/3177G06F11/0736G06F11/0754G06F11/079G06F11/3013G06F11/3495
Inventor 陈义强雷登云恩云飞方文啸郝立超黄云侯波陆裕东
Owner FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH