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A monitoring system and method for an ultra-fast inter-chip serial bus

A serial bus and monitoring system technology, applied in hardware monitoring, instrumentation, electrical digital data processing, etc., can solve problems such as poor stability of HSIC signaling, influence on SSIC signal integrity, and no effective solution for monitoring and testing devices

Active Publication Date: 2019-07-09
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The stability of HSIC signaling based on USB2.0 is poor, and the stability of SSIC whose rate has been increased several times is even worse. The printed circuit board (PCB) and test verification equipment used for connection will affect the signal integrity of SSIC
In the prior art, there is no effective solution for the monitoring and testing device of SSIC

Method used

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  • A monitoring system and method for an ultra-fast inter-chip serial bus
  • A monitoring system and method for an ultra-fast inter-chip serial bus
  • A monitoring system and method for an ultra-fast inter-chip serial bus

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Embodiment 1

[0067] The embodiment of the present invention provides a monitoring system for a serial bus between ultra-fast chips, figure 1 It is a schematic diagram of the composition structure of the monitoring system of the super-speed chip serial bus in the first embodiment of the present invention; as figure 1 As shown, the system includes: a USB device 11, a host device 12 and an analysis device 13; the USB device 11, the host device 12 and the analysis device 13 are electrically connected respectively;

[0068] The analysis device 13 is configured to obtain a first signal sent by the USB device 11 to the host device 12, and a second signal sent by the host device 12 to the USB device 11; analyze the first signal and the second signal, and determine the state of the transmission link between the USB device 11 and the host device 12 based on the analysis result.

[0069] In this embodiment, the USB device 11 is any device adopting the USB3.0 standard or higher standard (such as USB3...

Embodiment 2

[0074] The embodiment of the present invention also provides a monitoring system for a serial bus between ultra-fast chips, figure 2 It is a schematic diagram of the composition structure of the monitoring system of the serial bus between ultra-fast chips in the second embodiment of the present invention; as figure 2 As shown, the system includes: a USB device 11, a host device 12 and an analysis device 13; the USB device 11, the host device 12 and the analysis device 13 are electrically connected respectively;

[0075] Specifically, the USB device 11 includes: a USB controller 21, a bridge device 22 and a first physical layer device 23; the USB controller 21, the bridge device 22 and the first physical layer device 23 are electrically connected in turn ;

[0076] The USB controller 21 is configured to transmit a first PIPE3 signal to the bridge device 22;

[0077] The bridge device 22 is configured to bridge the first PIPE3 signal to the first physical layer device 23;

...

Embodiment 3

[0087] The embodiment of the present invention also provides a monitoring system for a serial bus between ultra-fast chips, image 3 It is a schematic diagram of the composition structure of the monitoring system of the serial bus between ultra-fast chips in the third embodiment of the present invention; as image 3 As shown, the system includes: a USB device 11, a host device 12 and an analysis device 13; the USB device 11, the host device 12 and the analysis device 13 are electrically connected respectively;

[0088] Specifically, the USB device 11 includes: a first USB controller 31, a bridge device 32, a first physical layer device 33 and a second physical layer device 35; the first USB controller 31, the bridge device 32 and The first physical layer device 33 is electrically connected in turn; the second physical layer device 35 is connected to the second end of the first USB controller 31 and the first end of the bridge device 32 through a first switch K1; The host devi...

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Abstract

A system and method for monitoring a serial bus between super-speed chips, and a computer storage medium. The system comprises: a universal serial bus (USB) device (11), a host device (12) and an analysis device (13). The USB device (11), the host device (12) and the analysis device (13) are electrically connected respectively. The analysis device (13) is configured to acquire a first signal sent by the USB device (11) to the host device (12) and a second signal sent by the host device (12) to the USB device (11), and analyse the first signal and the second signal, so as to determine a transmission link state between the USB device (11) and the host device (12) according to an analysis result.

Description

technical field [0001] The invention relates to digital circuit technology, in particular to a monitoring system and method for a serial bus between ultra-fast chips. Background technique [0002] With the development of Universal Serial Bus (USB, Universal Serial Bus) technology, the USB3.0 interface has been commonly used in electronic devices. The highest transfer rate of USB2. is 480Mbps, or 60MB / s. While USB 3.0 maintains compatibility with USB 2.0, it also provides the following enhanced functions: 1. The transmission rate is greatly improved, and the transmission rate of USB 3.0 can be as high as 5Gbps full-duplex. 2. Implemented better power management, supporting standby, hibernation and suspend states. 3. The USB3.0 standard requires that the power supply capacity of the USB3.0 interface is 1A, while that of USB2.0 is 0.5A. This enables the host to provide more power to the device, enabling the USB interface to charge terminals such as rechargeable batteries, LE...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/30G06F13/38
CPCG06F11/30
Inventor 周玉超
Owner SANECHIPS TECH CO LTD