Sequential control all-digital DLL control circuit and control method of NAND Flash controller

Abstract

The invention proposes a sequential control all-digital DLL control circuit and a control method of a NAND Flash controller. A DQS is delayed by 90 degrees through a delay locked loop, and is sent to a NAND Flash controller. Data is sampled from the middle, and is written into a memory array accurately and read from the array. The delay locked loop is composed of an all-digital circuit. Compared with the traditional analog DLL circuit, the all-digital circuit of the invention has the advantages of low power consumption, good portability and simple structure. The circuit can realize 90-degree phase delay, 180-degree phase delay or the like, and has self-regulation ability. The specific value of phase delay can be configured by application layer software through a CPU write register, a configured delay degree is realized by increasing or decreasing the number of stages of delay units in delay chains, and the flexibility of the delay locked loop is improved greatly. By configuring multiple delay chains, a timing delay signal needed for the NAND Flash controller to read, write and access NAND Flash particles of multiple channel memories is realized.

Description

Technical field [0001] The present invention relates to the field of NAND Flash memory, in particular to a timing control all-digital DLL control circuit and a timing control all-digital DLL control method for a NAND Flash controller. Background technique [0002] With the advent of the mobile Internet era, mobile terminals such as smart phones, tablet computers, handheld game consoles, and e-books have an increasing demand for non-volatile memory with large capacity, low power consumption and high reliability. As the king of non-volatile memory, NAND Flash has the advantages of large capacity and fast reading and writing speed, and is widely used. The most widely used SolidState Driver (solid state drive), its core technology is the NAND Flash controller, which realizes the read, write, and erase operations on NAND Flash memory particles. However, when accessing the NAND Flash memory, the standard NAND Flash particle interface timing must be followed to read and write data. [0...

AI Technical Summary

Problems solved by technology

[0004] At present, most DLL circuits adopt traditional analog circuit design, and its circuit structure, portability and flexibility are poor, and the design cost and hardware cost are relatively high.

Images