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Multi-channel high-speed AD system based on FPGA and PowerPC

A multi-channel, high-speed technology, applied in the direction of analog-to-digital converters, electrical components, code conversion, etc., can solve the problems that the synchronization index cannot meet the acquisition and processing of broadband signals, the sampling rate of the signal acquisition board is not high enough, and achieve hardware wiring errors Effects with large tolerance and high portability

Inactive Publication Date: 2017-02-01
CHENGDU GOLDENWAY ELECTRONICS
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AI Technical Summary

Problems solved by technology

The sampling rate of traditional signal acquisition boards is not high enough, and the SNR, SFDR and synchronization indicators cannot meet the requirements of broadband signal acquisition and processing, especially in the application of receiving equipment that requires synchronous processing of multi-channel signals. Unable to meet the current mainstream design requirements, therefore, a high-performance new sampling technology is urgently needed

Method used

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  • Multi-channel high-speed AD system based on FPGA and PowerPC
  • Multi-channel high-speed AD system based on FPGA and PowerPC
  • Multi-channel high-speed AD system based on FPGA and PowerPC

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Embodiment Construction

[0025] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0026] The present invention implements a high-speed acquisition circuit design based on FPGA to realize a high-speed synchronous acquisition system with 8 channels for each signal sub-board, a sampling rate of 1.25 GHz, and a quantization bit width of 10 bits. The system can work stably at 1.25 GHz sampling Frequency, inter-board and intra-board synchronization errors are within 80ps, which can be widely used in fields that require high sampling frequency and precise synchronization of multi-channel signals. It supports the use of DSP resources to process digital signals and use SERDES for synchronous transmission. At the same time, it has the characteristics of high portability and large error tolerance of hardware...

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Abstract

The invention relates to a multi-channel high-speed AD system based on an FPGA and a PowerPC. The system comprises a signal mother board based on the PowerPC and at least two signal daughter boards based on the FPGA, which are connected to the signal mother board, wherein the signal mother board provides synchronization pulse for the signal daughter boards, configuring ADC sampling parameters and sending an instruction of switching a synchronization operation and an actual sampling work mode; the signal daughter boards complete switching of the sampling operation mode and the synchronization operation according to the received instruction and transmit the collected data to the signal mother board through an SERDES interface, and the different signal daughter boards remain synchronous after the signal daughter boards return the data to the mother board. The system can stably work at a sampling frequency of 1.25 G, the synchronization error between the boards and in the boards can be within 80 ps, the system can be widely used in the fields with higher requirements for the sampling frequency and the need of precise synchronization of multi-channel signals, and meanwhile, the system has the characteristics of high transportability and large hardware routing error margin.

Description

technical field [0001] The invention belongs to the field of high-speed data acquisition, in particular to a multi-channel high-speed AD system based on FPGA and PowerPC. Background technique [0002] In the field of wireless communication and signal receiving and processing, the processing signal bandwidth is getting wider and wider, and the sampling rate of ADC is getting higher and higher. At the same time, the SNR (signal-to-noise ratio) and SFDR (spurious free dynamic range of In terms of A / D converters and D / A converters) and synchronicity and other performance indicators are increasingly demanding. The sampling rate of traditional signal acquisition boards is not high enough, and the SNR, SFDR and synchronization indicators cannot meet the requirements of broadband signal acquisition and processing, especially in the application of receiving equipment that requires synchronous processing of multi-channel signals. Can not meet the current mainstream design requirement...

Claims

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Application Information

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IPC IPC(8): H03M1/12
CPCH03M1/12H03M1/123
Inventor 刘宇波羊羽
Owner CHENGDU GOLDENWAY ELECTRONICS
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