A Multi-channel Parallel Acquisition System with Memory Synchronous Identification Function

Abstract

The invention discloses a multi-channel parallel acquisition system with the function of storage synchronous recognition. Among the N FPGA modules of the multi-channel parallel acquisition system, the first FPGA module generates an effective trigger signal according to the trigger signal of the trigger channel and sends it to The second FPGA module; each FPGA module in the 2nd to Nth FPGA modules is equipped with a delay module and a synchronization identification module respectively, and the synchronization identification module is used to sequentially determine the delay according to the serial number of the FPGA module when the multi-channel parallel acquisition system is initialized The delay value of the module is set. In actual work, the delay module receives the effective trigger signal of the previous FPGA module, and sends it to the trigger module after delaying according to the delay value, thereby generating an effective trigger signal. The invention accurately identifies and controls the effective trigger signals in each FPGA module in the multi-channel parallel acquisition system, thereby ensuring the correctness of the data sequence stored at the back end.

Description

technical field [0001] The invention belongs to the technical field of high-speed data acquisition, and more specifically relates to a multi-channel parallel acquisition system with a storage synchronization identification function. Background technique [0002] With the rapid development of science and technology, the frequency and bandwidth of digital signals also increase sharply, which puts forward higher requirements for the indicators of electronic measuring instruments. After using the time-alternating analog-to-digital conversion (TIADC) technology in parallel mode to successfully realize the high-frequency signal acquisition function of the high-speed acquisition system, how to stably store the generated high-speed data stream has become a problem for the stable operation of the acquisition system. one of the important research parts. [0003] The existing research on the synchronization problem of TIADC system mainly focuses on the reset synchronization problem be...

AI Technical Summary

Problems solved by technology

Before the read and write enable control of the data storage module, the effective trigger signal has to go through FPGA internal logic delay and circuit board delay, and these delay times are not easy to be accurately controlled, so the trigger signal is different from the internal operating clock of the system. source, it is possible that the trigger signal is just in the metastable interval of the running clock, which will lead to the uncertainty of the read and write control operations, and then cause data processing errors

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