Stacking and packaging structure for memory chips

Abstract

The invention relates to a stacking and packaging structure for memory chips. The stacking and packaging structure comprises a substrate with a two-sided signal layer, wherein a transfer board is connected between every two adjacent to-be-packaged chips; a window for wiring is formed in the middle of each transfer board; a welding point, close to the corresponding window, on each to-be-packaged chip passes through the window of the transfer board positioned above the chip to be welded on the transfer board through a gold wire; and the transfer boards and the substrate are welded through gold wires. By virtue of the transfer boards, the welding points are distributed from the centers of the chips to the peripheries, so that utilization of a wafer-level technological process is avoided, the technological difficulty is lowered and the cost is lowered consequently; in addition, the interconnection between chips and the transfer boards is realized firstly, so that the dimensions of the transfer boards can be set according to requirements; the dimensions of the transfer boards of the lower layer chips can be enlarged, so that perpendicular distribution of the gold wires and the upper layer chips is avoided; and furthermore, a special film, in which the gold wires can be embedded, is avoided, so that the cost is lowered and the technological difficulty is lowered.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and specifically refers to a memory chip stack packaging structure. Background technique [0002] With the vigorous development of the electronic industry and the continuous evolution of electronic technology, electronic products are also designed towards the trend of light, thin, short and small. With the increasing demand for miniaturization and high-operation technology, multiple chips will be integrated in one package structure to achieve more than twice the capacity or systemic functional requirements. For example, in the previous multi-chip stack package structure, it is Multiple chips are stacked and encapsulated in a packaging material. Ordinary chip solder joints are distributed on the edge of the chip, which is easy to solder with gold wires and realize stack packaging. difficulty. [0003] In general, memory chip products, common among known single-chip packaging tec...

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Problems solved by technology

[0006] In this package structure, both chips are stacked and packaged in a front-mounted way. However, in this stacked package structure, the solder joints of the two chips need to be redistributed, which belongs to the wafer rewiring process. Complete, high equipment and technical cost requirements, need to customize the mask, the price is expensive

In addition, in figure 2 In the stacked packaging structure, the film used to bond the upper and lower layers of chips can be embedded with gold wires, which is expensive, and the chip technology requires high precision in the chip (DIE Bond) process, which increases the difficulty of the process and realizes the cost. high

[0007] It can be seen that the above-mentioned known multi-chip packaging technology can double the memory chip capacity and increase the chip packaging density, but it is expensive and does not have the high function of high I / O density and low cost requirements.

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