FPGA system having Camera Link interface

A technology of interface and output port, which is applied in the field of FPGA system, can solve the problems of PLL resource consumption and poor portability, and achieve the effect of saving resources, avoiding phase inconsistency, and good scalability

Inactive Publication Date: 2017-02-22
BEIJING LUSTER LIGHTTECH
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  • Abstract
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  • Claims
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Problems solved by technology

[0007] The purpose of the embodiment of the present invention is to provide a kind of FPGA system with Camera Link interface, to solve existing FPGA system with Camera Link interface function, portability is relatively poor, and the problem that more consumes PLL resources

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  • FPGA system having Camera Link interface
  • FPGA system having Camera Link interface
  • FPGA system having Camera Link interface

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Embodiment Construction

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0024]The present invention provides a kind of FPGA system with Camera Link interface, in this FPGA system, be provided with PLL, data format converter and output parallel-to-serial conversion device, wherein, PLL is used for generating pixel clock and input preset clock wherein The pixel clock is a 7-multiplier clock, and the data form...

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Abstract

The invention discloses an FPGA system having a Camera Link interface. The system comprises a phase-locked loop, a data format converter and an output parallel-serial conversion device; the phase-locked loop is used for generating a pixel clock and a sevenfold frequency clock of the pixel clock from an input pre-set clock; the data format converter is used for outputting fixed data, and outputting target data after re-arranging input 28-bit parallel data; the output parallel-serial conversion device is used for outputting differential data and a differential clock after converting the target data and the fixed data according to the data bit width conversion ratio of 7:1 under the action of the pixel clock and the sevenfold frequency clock of the pixel clock; the differential clock and the differential data accord with specifications of a Camera Link standard protocol; the output end of the phase-locked loop is connected with the first input end of the output parallel-serial conversion device; and the output end of the data format converter is connected with the second input end of the output parallel-serial conversion device. By means of the system disclosed by the invention, a Camera Link protocol does not need to be customized in an IP core; and the transportability is relatively high.

Description

technical field [0001] The invention relates to the technical field of machine vision, in particular to an FPGA system with a Camera Link interface. Background technique [0002] The Camera Link interface is a relatively common data transmission interface in industrial cameras used in the machine vision industry. The Camera Link standard is developed from a Channel Link technical standard proposed by the National Semiconductor Laboratory (National Semi conductor). With an open interface protocol, the Camera Link standard adds 6 pairs of differential signal lines on the basis of the Channel Link standard that can transmit video digital signals, 4 pairs are used for parallel transmission of camera control signals, and the other 2 pairs are used for camera and image acquisition Serial communication between cards can also be used for serial communication between cameras and other image receiving and processing devices. [0003] The Camera Link interface of an industrial camera ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/77H04N5/232
CPCH04N5/77H04N23/66
Inventor 宋昱华姚毅
Owner BEIJING LUSTER LIGHTTECH
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