multi-chip structure

Abstract

The embodiment of the present invention discloses a multi-chip structure. One of the multi-chip structures may include: a switch system chip; a plurality of serial-to-parallel converter chips arranged around the switch system chip; and a plurality of inter-chip interfaces, wherein the plurality of inter-chip interfaces are used to connect all The plurality of serial-to-parallel converter chips are respectively connected to the switch system chip. Implementing the embodiments of the present invention, I / O chips can be independently designed to optimize their performance, and these I / O chips can be fabricated by the most suitable semiconductor process.

Description

[0001] This application claims priority to U.S. Provisional Patent No. 62 / 205,789 filed August 17, 2015, the entire contents of which are incorporated herein by this application. 【Technical field】 [0002] The invention relates to the technical field of semiconductors, in particular to a multi-chip structure. 【Background technique】 [0003] A traditional switch system on chip usually includes a serializer circuit / deserializer circuit (serial-to-parallel converter) (SerDes) to convert serial data to parallel data or convert parallel data to for serial data. In order to meet the next-generation switch SoC, the serial-to-parallel converter circuit needs to support multiple standards to meet the requirements of the system. However, designing a multi-standard serial-to-parallel converter in the switch SoC will cause many problems. First, the power loss of each serial-to-parallel converter circuit cannot be optimized at the same time, and the serial-to-parallel converter circuit ...

AI Technical Summary

Problems solved by technology

In order to meet the next-generation switch SoC, the serial-to-parallel converter circuit needs to support multiple standards to meet the system requirements, however, designing a multi-standard serial-to-parallel converter in the switch SoC will cause many problems

First, the power loss of each serial-to-parallel converter circuit cannot be optimized at the same time, and the serial-to-parallel converter circuit requires additional overhead to support different standards in the same circuit (for example, Non-Return-to-Zero (Non-Return-To- Zero, NRZ) standard and pulse amplitude modulation (Pulse-Amplitude Modulation, PAM) standard)

Secondly, the switch system chip adopts advanced (advanced) Complementary Metal-Oxide-Semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) technology manufacturing, for the core circuit, this CMOS technology is the best choice, but for high-speed serial and converters are not optimal

In addition, the core circuits of switch SoCs can be fabricated by low supply voltage process, for example, 10 nanometer (nm) process with 0.75 volt supply voltage, however, many serial-to-parallel converters should operate in a wide dynamic range, so , the low supply voltage process is not a good solution

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