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Method for erasing fefet memory circuit

A memory cell and voltage technology, applied in read-only memory, static memory, digital memory information, etc., can solve problems such as unwanted charge storage

Active Publication Date: 2019-02-26
纳姆实验有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] For example, in charge storage based transistors, cells adjacent to the cell being programmed may suffer from undesired charge storage

Method used

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  • Method for erasing fefet memory circuit
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  • Method for erasing fefet memory circuit

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Embodiment Construction

[0027] This paper describes a new technique for erasing ferroelectric field-effect transistor (FeFET) memory circuits comprising multiple FeFET memory cells, each FeFET comprising a gate stack, source, drain, channel, and bulk substrate region, wherein the gate stack includes a gate and a ferroelectric layer disposed between the gate and the channel. According to the inventive concepts described herein, an erase operation changes the threshold voltage of an n-channel or p-channel FeFET to a more positive or negative value, respectively. Furthermore, novel FeFETs are described having a charge storage layer arranged adjacent to the ferroelectric layer within the gate stack.

[0028] For an n-channel FeFET, a positive voltage is applied to the source and drain regions of at least one FeFET memory cell, and during application of the positive voltage to the source and drain regions of the FeFET memory cell, the gate region and The bulk substrate region is held at ground to cause e...

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Abstract

A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality of memory cells comprising FeFETs is described. Each FeFET includes a gate stack, a source, a drain, a channel, and a bulk substrate region, wherein the gate stack includes a gate and a ferroelectric layer disposed between the gate and the channel. Depending on the channel type, a positive or negative voltage is applied to the source and drain regions of at least one FeFET memory cell. During application of a positive voltage to the source and drain regions of the FeFET memory cell, the gate and bulk substrate region are maintained in a grounded state to cause erasure of at least one FeFET memory cell. Additionally, FeFETs are described having a charge storage layer disposed adjacent to a ferroelectric layer within a gate stack.

Description

Background technique [0001] Ferroelectric field effect transistors (FeFETs) have been envisioned and are still being investigated as ultra-low power non-volatile memory devices. However, by far the most prominent non-volatile transistor architecture is still represented by FLASH devices, which are a subset of charge storage (CS) based transistors. In this regard, CS-based transistors and FLASH devices can be considered to be the same "type" of device. When compared to these FLASH devices, FeFETs require only a fraction of the write voltage and can switch on a nanosecond regime. A write operation may mean programming a memory cell to a binary "0" or "off" state, or programming (erasing) a memory cell to a binary "1" or "on" state, respectively. The difference in write voltage between FeFETs and charge storage based transistors (FLASH devices) arises from fundamentally different underlying physical mechanisms for storing binary data. [0002] To represent a binary state, a FL...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/22
CPCG11C11/223H10B51/00H10B69/00H01L29/78391G11C11/2275G11C11/221G11C16/04
Inventor 斯特凡·费迪南德·米勒
Owner 纳姆实验有限责任公司