Method for forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as poor performance of semiconductor devices, achieve the effects of lower precision requirements, enhanced protection, and improved performance

Active Publication Date: 2017-04-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of semiconductor devices formed by prior art is poor

Method used

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  • Method for forming semiconductor device
  • Method for forming semiconductor device
  • Method for forming semiconductor device

Examples

Experimental program
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Embodiment Construction

[0023] As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

[0024] figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a , Figure 4b , Figure 5a , Figure 5b , Figure 6a and Figure 6b It is a structural schematic diagram of the process of forming a semiconductor device in the prior art.

[0025] combined reference figure 1 , Figure 2a and Figure 2b , Figure 2a for along figure 1 Sectional view obtained by cutting line A-A1 in the middle, Figure 2b for along figure 1 The cross-sectional view obtained by cutting lines B-B1 and C-C1 provides a semiconductor substrate 100, the semiconductor substrate 100 has an adjacent first region (I region) and a second region (II region), and the semiconductor substrate of the I region The surface of the bottom 100 has a first fin 120, the surface of the semiconductor substrate 100 in the II region has a second fin 121, and the surface of the semicon...

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Abstract

The invention discloses a method for forming a semiconductor device. The method includes the following steps: providing a substrate which has a first region and a second region which are adjacent to each other, the surface of the substrate having a gate electrode structure to stretch across the first region and the second region, the surface of the top of the gate electrode structure is covered with a protection layer; forming a first blockage layer which covers the first region and the second region; removing the protection layer of the second region and the first blockage layer on the surface of the substrate, forming a second side wall on the side wall of the gate electrode structure of the second region; following the formation of the second side wall, forming a second blockage layer which covers the first region and the second region; injecting ions to the first blockage layer and the second blockage layer; removing the protection surface of the first region and the first blockage layer and the second blockage layer after being injected with ions of the surface of the substrate, forming a first side wall on the side wall of the gate electrode structure of the first region. The method increases the properties of the semiconductor device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] MOS transistors are one of the most important semiconductor devices in modern integrated circuits. The basic structure of a MOS transistor includes: a substrate; a gate structure located on the surface of the substrate, a source region located in the substrate on one side of the gate structure, and a drain region located in the substrate on the other side of the gate structure. The working principle of the MOS transistor is: by applying a voltage to the gate structure, the current through the channel at the bottom of the gate structure is adjusted to generate a switching signal. [0003] In the existing MOS transistors, the substrate has a first region and a second region, the first region and the second region are used to form different types of MOS transistors, and the substrate surface has a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265H01L21/28
CPCH01L29/66477H01L21/265H01L21/28H01L21/28008
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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