31results about How to "No etch damage" patented technology

The invention discloses a trench structure for a power device and a manufacturing method thereof. The trench structure has the characteristics that: a side wall is vertical and provided with a thin silicon oxide film or a side wall is provided with a slight slope (theta=80-90 degrees) and a thin silicon oxide film; the bottom is smooth and is provided with a thick silicon oxide film; doped polycrystals are filled without gaps; boundary defects are eliminated; and the surface of a wafer at a trench position does not have any step or has a small step. The manufacturing method for the trench structure comprises the following steps of: forming the trench through dry etching; removing surface defects of the trench by using an oxidation process; forming the side wall of the trench by using a silicon nitride film; and forming a silicon oxide film with a thick bottom and a thin side wall in the trench through selective oxidation, wet etching and reoxidation; filling a good-conductivity polysilicon film without gaps; and removing the excessive polysilicon film outside the trench through etching or a chemically mechanical polishing process to form the trench structure required by a trench type power device. The manufacturing method is simple and stable in process, and is easy to implement; and the manufactured device has the advantages of small area, good electrical characteristics and the like.

The invention provides a manufacturing method and a manufacturing device of a printing magnetic orientation mother set and a magnetic pigment presswork. The manufacturing method of the printing magnetic orientation mother set comprises the following steps of: providing a magnetic body; utilizing a thermal radiation beam to heat a local area of the magnetic body, and forming a new domain structure in the local area through a self-magnetization manner of the magnetic body so as to change magnetic-field distribution of the local area; and removing the thermal radiation beam, so that the new domain structure reduced to be at normal temperature is kept, and further the changed magnetic-field distribution is kept in the local area so as to form the printing magnetic orientation mother set with preset magnetic orientation patterns. Through the method, the magnetic-field distribution is changed by utilizing thermal disturbance generated by the thermal radiation beam in the local area of the magnetic body, and the printing magnetic orientation mother set with the preset magnetic orientation patterns is further formed, so that the manufacturing process of the printing magnetic orientation mother set can be simplified, and abundant pattern information can be carried.

The invention relates to a manufacturing method using AlGaN / GaN-HEMT which can selectively revegetate. The method includes preparing a semiconductor main body (110) formed with a laminated structure, which cascades a cushion breaker (102) on a substrate (100), a UID-GaN layer on the cushion breaker, and a UID-AlGaN layer on the UID-GaN layer. The pattern of an insulating film (112) is formed on the first major face (111) of the surface of the semiconductor main body used as the UID-AlGaN layer in order to form a mask of an insulating film (112'). An etching process is not processed on the surface of the semiconductor main body,therefore an nSUP and / SUP-GaN layer selectively revegetates on the surface of the major face (111) of the semiconductor main body apart from the area of the insulating film. An ohm electrode is divided, a preconcerted area (117) is formed and the ohm electrode (122) is formed in the area of the selectively revegetated nSUP and / SUP-GaN layer. Then a preconcerted area (123) is formed and an opening is formed by dividing a gate electrode, and the gate electrode (124) is formed.

The invention discloses a method for forming a semiconductor device. The method includes the following steps: providing a substrate which has a first region and a second region which are adjacent to each other, the surface of the substrate having a gate electrode structure to stretch across the first region and the second region, the surface of the top of the gate electrode structure is covered with a protection layer; forming a first blockage layer which covers the first region and the second region; removing the protection layer of the second region and the first blockage layer on the surface of the substrate, forming a second side wall on the side wall of the gate electrode structure of the second region; following the formation of the second side wall, forming a second blockage layer which covers the first region and the second region; injecting ions to the first blockage layer and the second blockage layer; removing the protection surface of the first region and the first blockage layer and the second blockage layer after being injected with ions of the surface of the substrate, forming a first side wall on the side wall of the gate electrode structure of the first region. The method increases the properties of the semiconductor device.

The invention relates to a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a first conductive layer extending in a first direction and being arranged in a second direction, forming initial magnetic tunnel structures on the surface of the first conductive layer and the surface of the substrate; forming a first trench and a second trench in the initial magnetic tunnel structure, the second trench extending in a first direction, the first trench being located between adjacent second trenches, the first trench extending in a second direction, the first trench having a first size in the first direction, the second trench having a second size in the second direction, the first size being smaller than the second size; forming mask layers in the first trench and on the surfaces of the side walls of the second trench, the first trench is filled with the mask layers; and etching the initial magnetic tunnel structures by taking the mask layers as masks until the surface of the substrate is exposed, and forming a magnetic tunnel structure on the surface of the first conductive layer. The semiconductor structure formed by the method is good in performance.

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a first electromagnetic film on the substrate,wherein the surface of a part of the first electromagnetic film is provided with a tunnel layer and a second electromagnetic layer located on the surface of the tunnel layer; forming a first dielectric film on the surface of the first electromagnetic film, the surface of the side wall of the tunnel layer, and the surfaces of the side wall and the top of the second electromagnetic layer; forming asecond dielectric layer on the surface of the first dielectric film located at the top of the second electromagnetic layer; etching back the first dielectric film by using a first etching process until the surface of the first electromagnetic film is exposed, and forming a first dielectric layer on the surface of the side wall of the tunnel layer and the surfaces of the top and the side wall of the second electromagnetic layer, wherein the etching rate of the first etching process on the first dielectric film is higher than the etching rate of the first etching process on the second dielectriclayer; and etching the first electromagnetic film by taking the first dielectric layer and the second dielectric layer as masks until the surface of the substrate is exposed, thereby forming a firstelectromagnetic layer. The semiconductor structure formed by the method is good in performance.

The invention provides a self-aligned quadruple pattern technology (SAQP for short). According to the SAQP of the invention, through the secondary deposition process of side wall materials, on the premise that the current photoetching technology is not changed at all (that is, the size of a photoetching window is kept unchanged), the minimum size of 1 / 4 pitch can be obtained. Compared with the original self-aligned double-pattern technology (SRDP) wherein the minimum size of only 1 / 2 pitch can be obtained, the performance of the minimum size is greatly improved. As a result, the density of a semiconductor integrated circuit can be greatly improved.

The invention discloses a method for achieving isolation of a semiconductor device. According to the method, a thermal oxidation technology is combined with a deposition technology; an active region of the semiconductor device is firstly formed; a high depth-to-width ratio gap is filled to form narrow STI isolation; and a low depth-to-width ratio gap is finally filled to form wide STI isolation. The method has the advantages that the method has excellent gap filling ability for a micron-scale gap or the high depth-to-width ratio gap with a sub-45nm technology node, the filling quality is good and no hole or crack is generated; the filling rate is high, stable and controllable; an etching damage of an HDP-CVD to a substrate is avoided; and the method does not depend on the shape and form of the section of the gap, and is completely compatible with a bulk silicon CMOS process, simple in process and low in cost.

The invention provides a semiconductor component and its forming method wherein the method comprises: providing a substrate whose surface is provided with a plurality of separately arranged initial metal grid electrodes, side walls at the side walls of the initial metal grid electrodes, and a first interlayer dielectric layer covering the substrate surface and the side walls at the side walls of initial metal grid electrodes with the top surface of the first interlayer dielectric layer leveled with the top surfaces of the initial metal grid electrodes; etching the initial metal grid electrodes to form target metal grid electrodes wherein the middle parts of the target metal grid electrodes are higher than the edge parts; forming a protection layer covering the target metal grid electrodes wherein the surface of the protection layer is leveled with the top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer covering the first interlayer dielectric layer, the side walls and the protection layer; and forming self-aligning contact holes that penetrate the thicknesses of the first interlayer dielectric layer and the second interlayer dielectric layer between adjacent target metal grid electrodes. The method of the invention is capable of increasing the performance of the semiconductor.

The invention provides an etching method of an organic film and a repairing method of a circuit in a display area of ​​a display substrate. The etching method of the organic film includes etching the position to be etched of the organic film by means of a focused ion beam; In the etching method of the organic film, water vapor is fed to the surface to be etched during the process of etching the organic film by the focused ion beam, so that the position to be etched of the organic film can be etched quickly in a targeted manner, and the During the etching process, it will not cause etching damage to other non-etching positions of the organic film, thereby solving the problem of non-etching positions being damaged by etching caused by the existing concentrated sulfuric acid etching, and also speeding up the etching process. speed.

A 3D NAND memory and its forming method. In the forming method, before the sacrificial layer is filled in the first channel hole, a hole expansion step is performed to increase the width of the opening of the first channel hole. Through the hole expansion step, the width of the opening of the first channel hole is increased, and the second stack structure is subsequently formed on the first stack structure, even if the position of the second channel hole formed in the second stack structure is relative to the first There is a certain positional offset of the channel hole, and the bottom position of the second channel hole can still fall in the widened opening of the first channel hole, which reduces the gap between the first channel hole and the second channel hole. It is difficult to form the memory structure, and since the hole expansion step is performed before filling the sacrificial layer in the first channel hole, only one step of filling the sacrificial layer is required before forming the second stacked structure, which simplifies the process steps.

The invention discloses a semiconductor device forming method. The method comprises steps that: a base comprising a first area and a second area is provided, wherein the first area base and the secondarea base are provided with first oxidation layers; an etching process is carried out to etch and remove the first oxidation layer with a first thickness in the first area; after the etching processis carried out, the remaining first oxidation layer in the first area is subjected to a cleaning process; the etching process and the cleaning process are carried out alternatively until the first oxidation layer in the first area is removed; and a second oxidation layer is formed on the first area base, wherein the thickness of the second oxidation layer is different from that of the first oxidation layer. The first area base can be prevented from being etched and damaged, the first area base can thus keep a good surface morphology, and the electrical performance of the formed semiconductor device is improved.

A formation method of a semiconductor structure comprises the steps of providing a substrate in which a bottom-layer metal layer is formed; forming an etching barrier layer covering the surfaces of the substrate and the bottom-layer metal layer; forming a dielectric layer covering the surface of the etching barrier layer; forming an opening penetrating the dielectric layer, and exposing the surface of the etching barrier layer out of the bottom of the opening; adopting a dry etching process of an etching gas containing CF3I to etch a part of thickness of etching barrier layer located at the bottom of the opening, and forming a protection layer on the surface of the side wall of the opening while etching the part of thickness of etching barrier layer; after the protection layer is formed, adopting an isotropy dry etching process to etch and remove the residual thickness of etching barrier layer until the top surface of the bottom-layer metal layer is exposed; forming a conductive layer on the surface of the exposed bottom-layer metal layer, wherein the conductive layer fills the opening. According to the present invention, the etching damage to the bottom-layer metal layer is reduced, and the electrical property of the semiconductor structure is improved.

A 3D NAND memory and its forming method, the forming method, before forming the stack structure, a semiconductor epitaxial layer is formed in the groove, when forming the semiconductor epitaxial layer, the forming process will not be affected by the depth of the through hole in the stack structure , size and shape, so that the surface of the formed semiconductor epitaxial layer has a flat surface, so that the channel layer in the storage structure and the semiconductor epitaxial layer can have good contact performance. In addition, the surface of the formed semiconductor epitaxial layer is lower than the surface of the dielectric layer, so that the formed etching stop layer (especially when the etching stop layer is made of metal material) can be limited in the groove above the semiconductor epitaxial layer, so that the etching The stop layer can maintain high position accuracy, and make the dielectric layer have a flat surface, which facilitates subsequent formation of a stacked structure.

The invention discloses a method for forming a semiconductor device. The method includes the following steps: providing a substrate which has a first region and a second region which are adjacent to each other, the surface of the substrate having a gate electrode structure to stretch across the first region and the second region, the surface of the top of the gate electrode structure is covered with a protection layer; forming a first blockage layer which covers the first region and the second region; removing the protection layer of the second region and the first blockage layer on the surface of the substrate, forming a second side wall on the side wall of the gate electrode structure of the second region; following the formation of the second side wall, forming a second blockage layer which covers the first region and the second region; injecting ions to the first blockage layer and the second blockage layer; removing the protection surface of the first region and the first blockage layer and the second blockage layer after being injected with ions of the surface of the substrate, forming a first side wall on the side wall of the gate electrode structure of the first region. The method increases the properties of the semiconductor device.

The invention discloses a method for achieving isolation of a semiconductor device. According to the method, a thermal oxidation technology is combined with a deposition technology; an active region of the semiconductor device is firstly formed; a high depth-to-width ratio gap is filled to form narrow STI isolation; and a low depth-to-width ratio gap is finally filled to form wide STI isolation. The method has the advantages that the method has excellent gap filling ability for a micron-scale gap or the high depth-to-width ratio gap with a sub-45nm technology node, the filling quality is good and no hole or crack is generated; the filling rate is high, stable and controllable; an etching damage of an HDP-CVD to a substrate is avoided; and the method does not depend on the shape and form of the section of the gap, and is completely compatible with a bulk silicon CMOS process, simple in process and low in cost.

The invention method relates to wet corrosion technology used to obtain sapphire substrate with particular graph structure, then bridging epitaxial growth technology is used to deposit GaN bridging epitaxial layer and required component structure layer. By the invention, problem of lattice orientation tilting of epitaxial material produced by prior ELOG and CE technology, penetration dislocation density in GaN substrate epitaxial layer is reduced.

The invention provides a semiconductor device and a forming method thereof. By preferentially preparing the metal ring, the piezoelectric layer covers the metal ring, so that the metal ring will not be exposed from the surface of the piezoelectric layer, thereby avoiding damage to the metal ring when preparing the mass load layer, and can effectively improve the quality The limitation of the process of the load layer and the flexible adjustment of the order of the mass load layer and the upper electrode layer also improve the manufacturing efficiency of the device.

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which is provided with a first dielectric layer, the first dielectric layer is internally provided with a first conductive layer, and the first dielectric layer exposes the top of the first conductive layer; the second dielectric layer is positioned on the first dielectric layer; the second conducting layer is located in the first dielectric layer and the second dielectric layer, and the second conducting layer is located on the top surface and part of the side wall surface of the first conducting layer. The second conducting layer is not only located on the top surface of the first conducting layer, but also located on the surface of the partial side wall of the first conducting layer, so that the contact area between the first conducting layer and the second conducting layer is increased, and the electrical performance of the formed semiconductor structure is improved.