Formation method of semiconductor structure

Abstract

A formation method of a semiconductor structure comprises the steps of providing a substrate in which a bottom-layer metal layer is formed; forming an etching barrier layer covering the surfaces of the substrate and the bottom-layer metal layer; forming a dielectric layer covering the surface of the etching barrier layer; forming an opening penetrating the dielectric layer, and exposing the surface of the etching barrier layer out of the bottom of the opening; adopting a dry etching process of an etching gas containing CF3I to etch a part of thickness of etching barrier layer located at the bottom of the opening, and forming a protection layer on the surface of the side wall of the opening while etching the part of thickness of etching barrier layer; after the protection layer is formed, adopting an isotropy dry etching process to etch and remove the residual thickness of etching barrier layer until the top surface of the bottom-layer metal layer is exposed; forming a conductive layer on the surface of the exposed bottom-layer metal layer, wherein the conductive layer fills the opening. According to the present invention, the etching damage to the bottom-layer metal layer is reduced, and the electrical property of the semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous advancement of VLSI process technology, the feature size of semiconductor devices has been continuously reduced, and the chip area has continued to increase. The delay time of the interconnect structure can be compared with the device gate delay time. People are faced with the problem of how to overcome the significant increase in RC (R refers to resistance, C refers to capacitance) delay due to the rapid increase in connection length. In particular, due to the increasing influence of the capacitance between metal wirings, the performance of the device is greatly reduced, which has become a key restrictive factor for the further development of the semiconductor industry. In order to reduce the RC delay caused by interconnection, various measures have been adopted...

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Problems solved by technology

[0004] However, the electrical properties of semiconductor structures formed by existing technologies still need to be improved

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