Semiconductor component and its forming method

Abstract

The invention provides a semiconductor component and its forming method wherein the method comprises: providing a substrate whose surface is provided with a plurality of separately arranged initial metal grid electrodes, side walls at the side walls of the initial metal grid electrodes, and a first interlayer dielectric layer covering the substrate surface and the side walls at the side walls of initial metal grid electrodes with the top surface of the first interlayer dielectric layer leveled with the top surfaces of the initial metal grid electrodes; etching the initial metal grid electrodes to form target metal grid electrodes wherein the middle parts of the target metal grid electrodes are higher than the edge parts; forming a protection layer covering the target metal grid electrodes wherein the surface of the protection layer is leveled with the top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer covering the first interlayer dielectric layer, the side walls and the protection layer; and forming self-aligning contact holes that penetrate the thicknesses of the first interlayer dielectric layer and the second interlayer dielectric layer between adjacent target metal grid electrodes. The method of the invention is capable of increasing the performance of the semiconductor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] The MOS (metal-oxide-semiconductor) transistor is an important semiconductor device. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate; a semiconductor substrate located on one side of the gate structure The source region and the drain region in the semiconductor substrate on the other side of the gate structure. [0003] As the feature size is further reduced, the distance between adjacent gate structures is reduced, so that the process of forming contact holes for connecting the source region, the drain region and the upper metal line in the gap between the above gate structures It becomes more difficult, so the formation process of self-aligned contact holes is introduced. [0004] At ...

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Problems solved by technology

[0005] However, the performance of semiconductor devices formed in the prior art is poor

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