Unlock instant, AI-driven research and patent intelligence for your innovation.

"Read" Test Benchmark Establishment Method for Embedded eeprom

An establishment method and embedded technology, applied in the direction of static memory, instrument, etc., can solve the problem of increasing the chip area, etc., and achieve the effect of simple interface, low overhead, and high circuit reuse rate

Active Publication Date: 2020-01-10
SHANGHAI HUAHONG INTEGRATED CIRCUIT
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The cost of CP testing: the increased chip area of ​​the built-in test circuit and the rental of equipment during the test process are important factors of product cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • "Read" Test Benchmark Establishment Method for Embedded eeprom

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0009] to combine figure 1 As shown, the "reading" test benchmark establishment method of the embedded EEPROM is based on the SoC's own architecture, utilizing its own circuit modules, such as CPU (Central Processing Unit, central processing unit), communication ports, EEPROM and other modules, Based on the SoC's own communication channel, the scan of the read current reference and the EEPROM read test are realized. The whole process only involves basic register settings, reading and writing of EEPROM, all data interaction is digital and does not involve the collection of analog data, and the entire data interaction is based on the necessary instructions of the SoC itself, which will not increase the cost of the SoC. Instruction set, software overhead on SoC is also very small.

[0010] The read current window can clearly reflect the read redundancy (product quality) and manufacturability (process redundancy) of the EEPROM Cell.

[0011] The establishment of the read current...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for building a ''read'' testing benchmark of an embedded EEPROM. The method comprises the steps of generating a group of read reference current through proportional division on the basis of read current of a standard Cell of the EEPROM, testing a failure ratio of the EEPROM under various reference current configurations while scanning proportional division parameters and indirectly measuring a read window of the EEPROM; and obtaining the final ''read'' testing benchmark of the EEPROM by combining product process control parameters and a reliability check result of the EEPROM on the basis of obtained read window data. Therefore, the quality of a finished product and the wafer manufacturing process redundancy are ensured, and meanwhile, the production cost of the product is reduced.

Description

technical field [0001] The present invention relates to the field of integrated circuit testing, in particular to an embedded EEPROM (Electrically Erasable Programmable Read-Only Memory, electrically erasable non-volatile memory) "reading" test benchmark establishment method, which is applicable to embedded EEPROM CP ( Chip Probing (chip detection) test is established for the screening benchmark of the EEPROM read process. Background technique [0002] A reasonable CP test benchmark is a necessary condition for the quality of the finished product, and it is also a necessary condition for the stability of the product yield. The cost of CP testing: the increased chip area of ​​the built-in test circuit and the equipment rental during the test process are important factors of product cost. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for establishing a "reading" test standard of an embedded EEPROM, whic...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56G11C2029/5006
Inventor 孙卫红
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com