Semiconductor structure and forming method therefor

Abstract

The invention discloses a semiconductor structure and a forming method therefor. The forming method for the semiconductor structure comprises the following steps: a substrate having a nominal grid electrode is provided, source-drain areas are formed at two sides of the nominal grid electrode on the substrate, the source-drain areas are doped with deuterium, the nominal grid electrode is removed, a grid electrode structure having a gate oxide layer is formed at the position of the nominal grid electrode, and the deuterium enters the gate oxide layer. The semiconductor structure is therefore obtained, the deuterium is enabled to enter the gate oxide layer, a stable covalent bond is formed on an interface of the gate oxide layer, a problem of dangling bonds can be effectively alleviated, recovery capability of a device confronted with hot carrier's effect can be improved, and effects exerted on performance of the device by the hot carrier's effect can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] At present, semiconductor manufacturing technology has been developed rapidly. Such as Figure 1-6 A common MOS formation process in the prior art is shown. include: [0003] Such as figure 1 As shown, a gate structure 2 is formed on a substrate 1; [0004] Such as Figure 2-Figure 4 As described above, deposit a protective layer 3 on the substrate 1 to cover the gate structure 2; perform reactive ion etching to remove part of the protective layer 3, and make the protective layer 3 inclined at both sides of the gate structure 2; further removing the part of the protective layer 3 located on the substrate 1 to form a gate spacer 4; [0005] Such as Figure 5 As shown, the source and drain electrodes 5 are epitaxially formed on both sides of the gate 2 on the substrate 1, and are...

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Problems solved by technology

[0007] However, including but not limited to the semiconductor structure formed through the above steps, dangling bonds will be formed inside. These dangling bonds mainly occur on the surface or interlayer interface, which will cause holes, dislocations, and the introduction of other impurities. situation

[0008] In addition, in the current MOS manufacturing process, another issue that arises is the impact of hot carrier effects on device performance

Special attention is paid to the fact that in smaller-sized devices, when they are used at higher voltages, the carriers in the channel will enter the insulating layer because they have enough energy, thus affecting the performance of the device

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