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A method for avoiding gate polysilicon etching dent defect

A technology of polysilicon and polysilicon layer, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve problems such as product failure, lower yield, waste, etc., and achieve the effect of avoiding gate polysilicon etching dent defects

Active Publication Date: 2019-09-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, as mentioned above, in some cases, dent defects will be found on the etched polysilicon, and this defect will lead to product failure, reduce yield, and cause waste

Method used

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  • A method for avoiding gate polysilicon etching dent defect
  • A method for avoiding gate polysilicon etching dent defect
  • A method for avoiding gate polysilicon etching dent defect

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Embodiment Construction

[0027] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0028] The inventors of the present invention have found that the root cause of pit defects on etched polysilicon is that the first layer in the hard mask on the polysilicon layer is relatively too thin to protect the polysilicon layer throughout the polysilicon etch process , resulting in polysilicon dent defects.

[0029] The present invention is proposed based on the above analysis, wherein the thickness of the second layer in the hard mask on the polysilicon layer is dynamically adjusted according to the thickness of the oxide layer in the hard mask on the polysilicon layer, thereby avoiding gate polysilicon etching dents defect.

[0030] The specific preferred embodiments of the present invention will be described below in conjunction with...

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Abstract

The invention provides a method for avoiding the etching dent defect of grid polycrystalline silicon. The method comprises the following steps of: (1), forming a first hard mask group sub-layer on a polycrystalline silicon layer, wherein the first hard mask group sub-layer is a constituent part used for etching a hard mask of the polycrystalline silicon layer; and the first hard mask group sub-layer has the first thickness; and (2), forming a second hard mask group sub-layer on the first layer, wherein the second hard mask group sub-layer is another constituent part used for etching the hard mask of the polycrystalline silicon layer; the second hard mask group sub-layer has the second thickness; and the second thickness is set according to the first thickness. In the method for avoiding the etching dent defect of the grid polycrystalline silicon provided by the invention, the thickness of the second layer in the hard mask on the polycrystalline silicon layer is dynamically adjusted according to the thickness of an oxide layer in the hard mask on the polycrystalline silicon layer; and, the etching dent defect of the grid polycrystalline silicon can be effectively avoided in a condition that the technological operation does not need to be changed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for avoiding pitting defects of gate polysilicon etching. Background technique [0002] In the 0.15 process, after the polysilicon is etched, pit defects are sometimes found on the etched polysilicon. Specifically, the polysilicon etching method according to the prior art generally includes: a step of forming a photoresist pattern, a step of forming a hard mask pattern, and a step of forming a polysilicon pattern. [0003] figure 1 A schematic view schematically showing the photoresist pattern forming steps of the polysilicon etching method according to the prior art. like figure 1 As shown, an oxide layer 21, a SION layer 22 (the oxide layer 21 and the SION layer 22 form a hard mask) and a photoresist layer 30 are sequentially formed on the polysilicon layer 10, and a photoresist pattern is formed. figure 2 A schematic view ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3213
Inventor 曹子贵
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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