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FPGA chip wiring method

A wiring method and wiring technology, applied in the direction of instruments, calculations, electrical digital data processing, etc., can solve the problem of not increasing the wiring speed, and achieve the effect of reducing time delay and improving wiring speed

Active Publication Date: 2017-05-24
CAPITAL MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] With the expansion of the scale of FPGA chips, the requirements for wiring speed are getting higher and higher. At present, the industry has not provided a method to improve the wiring speed.

Method used

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Embodiment Construction

[0018] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all the embodiments.

[0019] The embodiment of the present invention provides an FPGA chip wiring method, which analyzes the characteristics of the wiring module of the FPGA chip architecture and performs reasonable pruning to increase the wiring speed and reduce the time delay.

[0020] figure 1 It is a schematic flowchart of a method for wiring an FPGA chip provided by an embodiment of the present invention. Such as figure 1 As shown, an FPGA chip wiring method includes steps S101-S103:

[0021] Step S101: Perform FPGA chip layout and obtain the coordinates of...

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PUM

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Abstract

The present invention relates to an FPGA chip wiring method. The method comprises: carrying out FPGA chip layout and obtaining coordinates of each unit of the chip after layout; according to a wiring pattern of the FPGA chip, obtaining pre-stored wiring code information corresponding to the pattern; and determining the code of the unit according to the coordinates of each unit after layout, and carrying out wiring pruning on each unit according to the wiring code information. According to the method disclosed by the present invention, by obtaining the wiring code information of the wiring pattern in the FPGA chip, and according to the pre-stored wiring code information, reasonable pruning is carried out in the actual wiring process, so that the wiring speed is improved, and the time delay is reduced.

Description

Technical field [0001] The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to an FPGA chip wiring method. Background technique [0002] FPGA is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurability. These features make FPGAs have been more and more widely used in many fields such as data processing, communication, and networking. [0003] At present, in Field Programmable Gate Array (FPGA) applications, integrated circuits are required to have a programmable or configurable interconnection network, and logic gates are connected to each other through the configurable interconnection network. FPGA, which functions as an independent chip or the core part of the system, has been widely used in a large number of microelectronic devices. The broad definition of FPGA logic gates not only refers to simple NAND gates, but also refers to logic elements (LE...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 刘桂林
Owner CAPITAL MICROELECTRONICS
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