Short time interval modulation domain measure sequential design method

Abstract

The invention provides a short time interval modulation domain measure sequential design method; a measuring data output time arranging unit, each data valid series-parallel mechanism unit, a measuring valid feedback signal forming unit and an operation processing unit are provided; the measuring data output time arranging unit can arrange various parameter data according to the time sequence, wherein the parameter data is obtained in one measurement of each measuring unit, and each data valid series-parallel mechanism unit is designed according to said sequence; the data valid series-parallel mechanism units build a series-parallel process for the sequence relation of the outputted measuring parameters, and select the time of the last outputted measuring data as the end of a valid measuring process; the measuring valid feedback signal forming unit uses a feedback signal to start the measuring unit; the operation processing unit is used for realizing an algorithm, realizing gapless integration of the data measured by high-low gate two measuring channels, using a high speed interface to read the measured data, and carrying out final operation, processing and displaying of the data.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a timing sequence design method for short time interval modulation domain measurement. Background technique [0002] In the field of electronic measurement, with the development and application of pulse modulation, digital modulation, linear modulation, and frequency-agile modulation technologies, higher requirements are placed on modern modulation domain analyzers. In order to meet new requirements, modern modulation domain analysis needs to have measurement requirements such as shorter sampling interval, larger analysis bandwidth, and higher resolution. Modulation domain analysis accurately characterizes the transient characteristics of the signal under test through high-speed continuous measurement without dead zone. The typical measurement sequence diagram is as follows: figure 1 shown. [0003] figure 1 Among them, the synchronous gate Ts is generated after synchronizing ...

AI Technical Summary

Problems solved by technology

However, since the determination of the delay time is still based on the low gate as the time reference, the size of the gate must be greater than ΔT0 to meet the processing of the delay time of ΔT0, that is to say, ΔT0 limits the gate design and cannot be less than ΔT0

Moreover, there is a certain time error in the actual circuit. In the actual test, the value of ΔT0 will fluctuate in a small range according to the time of retriggering. Therefore, the delay time setting should be larger than ΔT0, and the measurement time will be further increased.

[0010] Therefore, according to the method of processing high gate channel data during low gate period and processing low gate channel data during high gate period, the time interval of modern technical solutions for modulation domain analysis is limited to more than 100 ns, or even higher, which also restricts the short time of modulation domain analysis. Interval requirements for frequency-agile and linear-frequency measurements

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