Semiconductor device
A technology of semiconductor and time slot configuration, applied in static memory, instrument, electrical digital data processing, etc., can solve problems such as delay degradation, follow-up requests cannot flow, etc., and achieve the effect of improving delay, preventing request stagnation, and reducing circuit size
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no. 1 example
[0038] figure 1 is a diagram showing the configuration of the semiconductor device according to the first embodiment. Such as figure 1 As shown in , the semiconductor device according to the first embodiment includes a plurality of masters 100, a plurality of sub-bus controllers 200a, a bus arbiter 300, a memory controller 400a, a memory 500, a central bus controller 600a, a bus 10, a bus 20 and bus 30. Although in figure 1 The number of master controllers 100 is three in the example shown in , but the number of master controllers 100 is not limited and may be any number equal to or greater than two. figure 1 The three masters 100 shown in are referred to as master A, master B and master C. In addition, the number of master controllers 100 is the same as the number of sub-bus controllers 200a.
[0039] A plurality of masters 100 are connected to respective sub-bus controllers 200 a via a bus 10 . The plurality of masters 100 output requests for the memory 500 to the resp...
no. 2 example
[0074] Next, a semiconductor device according to a second embodiment will be described. Such as Figure 5 As shown in , the semiconductor device according to the second embodiment includes a plurality of masters 100, a plurality of sub-bus controllers 200a, a bus arbiter 300, a memory controller 400b, a memory 500, a central bus controller 600b, a bus 10, a bus 20 and bus 30. Since the configurations of the plurality of masters 100, the plurality of sub-bus controllers 200a, the bus arbiter 300, the memory 500, the bus 10, the bus 20, and the bus 30 are the same as those shown in the first embodiment, descriptions thereof will be omitted. description of.
[0075] Next, refer to Figure 6 , the central bus controller 600b will be described. Such as Figure 6As shown in , the central bus controller 600b includes a maximum authorized number configuration register 601, an authority authorization number controller 602, an authority authorization selection controller 603b, a ti...
no. 3 example
[0139] Next, a third embodiment will be described. In the third embodiment, a central bus controller 600d is used instead of the central bus controller 600b of the second embodiment. Since the configuration other than that of the central bus controller is the same as that shown in the second embodiment, description thereof will be omitted.
[0140] Next, refer to Figure 15 , the central bus controller 600d will be described. Such as Figure 15 As shown in , the central bus controller 600d includes a maximum authorized number configuration register 601, an authority authorization number controller 602, an authority authorization selection controller 603d, a time slot configuration register 604, a refresh request sub-slot number configuration register 605, a refresh request Controller 606, allocation priority calculation circuit 608, best effort (BE) register set 630, and delivery monitor 640a. Since the configurations of the authorized maximum number configuration register...
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