Fabrication method of trench double-layer gate mosfet

Abstract

The invention discloses a method for manufacturing a trench-type split gate MOSFET. The method comprises the following steps: 1) etching a trench and growing the TCH liner of an ONO structure; 2) growing source polysilicon and performing reverse etching to the upper surface of the trench; 3) protecting a source polysilicon link area by using photoresist, and performing reverse etching on source polysilicon in a cell area; (4) successively removing the partial outer layer silicon oxide film in the TCH liner, the photoresist, and the remaining outer layer silicon oxide film in the TCH liner; 5) growing the oxide layer between the polysilicon; 6) removing the silicon nitride film and the inner layer silicon oxide film in the TCH liner; 7) successively growing a gate oxide layer, gate polysilicon, and performing reverse etching on the gate polysilicon to complete the device production. The method, by optimizing a TCH liner removal process and reducing the oxidation amount of the source polysilicon, improves the IPO layer appearance of the source polysilicon link area and solves the residue of the gate polysilicon so as to eliminate a gate-to-source electric leakage hazard.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a trench type double-layer gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Background technique [0002] The structure and appearance of the dense area (Cell area) and the source polysilicon linkup area (Source poly linkup area) of the existing 100V trench type double-layer gate (Split Gate) MOSFET device are as follows: figure 1 As shown, the lower layer of the trench is the source polysilicon, the upper layer is the gate polysilicon, and the side wall of the trench is a trench layer junction film (TCH liner), and the trench layer junction film is ONO (silicon oxide film-silicon nitride film -silicon oxide film) structure, an IPO layer (inter-polysilicon oxide, oxide layer between polysilicons) is formed between the gate polysilicon and the source polysilicon, and the IPO layer is formed by oxidizing the source polysilic...

AI Technical Summary

Problems solved by technology

[0003] Due to the thickness requirements of the trench layer junction film in the conventional trench type double-layer gate MOSFET device structure That is, the oxidation thickness of the IPO layer is required to be thick enough, which leads to uncontrollable morphology of the source polysilicon, such as figure 1 As shown in (b) in (b), the top of the source polysilicon is relatively steep, and the curvature on both sides of the top of the IPO layer is relatively large (the part outlined by the dotted line in the figure), resulting in the gate polysilicon residue often remaining at the lead-out end of the source polysilicon, thus Causes leakage from the gate to the source, creating a hidden danger of current short circuit

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