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Processor and method for detecting self-modifying code

A processor and self-correcting technology, applied in the field of detecting self-correcting program codes, can solve problems such as troublesome self-correcting program codes, and achieve the effect of improving performance

Active Publication Date: 2019-03-15
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But even a 1KB ownership block is enough to cause problems for self-modifying code in many cases

Method used

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  • Processor and method for detecting self-modifying code
  • Processor and method for detecting self-modifying code
  • Processor and method for detecting self-modifying code

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0022] The inventors discovered memory ownership issues due to self-modifying code. They developed an ownership queue that builds memory ownership by cache line to detect self-correcting code.

[0023] figure 1 is a simplified functional block diagram of the processor 100 combined with an ownership queue (OWNQ) 101 . Ownership queue 101 is implemented in accordance with one embodiment to establish ownership between data and instructions. The standard instruction set architecture (instruction set architecture, ISA) of the processor 100 may be an x86 macro (macro) architecture. The x86 macroarchitecture can correctly execute most applications designed to run on an x86 processor. An application is executed correctly when its expected results are achieved. In particular, the processor 100 executes instructions in the x86 instruction set and has an x86 user-visible register set. However, the present invention is not limited to the x86 architecture, and the processor 100 can be...

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Abstract

The invention relates to a processor and method for detecting self-correcting program code. The processor and method determine the memory ownership based on the cache line to detect a self-correcting program code with cyclic instructions. The ownership queue has multiple storage units to determine the memory ownership based on the cache line. The ownership index and the winding bits of each cache line in the ownership queue are determined, and the instructions generated from the same cache line are provided to the ownership queue. When the instruction is raised to execute, the ownership index in the instruction is accessed by the corresponding storage unit in the ownership queue. The overwrite of the fetch line is detected when the instruction does not match the winding bits in the storage unit. The instruction is marked to produce a first exception event, and the first exception event is executed when the instruction is about to exit. The first exception event refreshes the processor to prevent the instruction from exiting and re-fetches the instruction for continuous processing. The processor and method for detecting self-correcting program code can improve the performance of the processor.

Description

technical field [0001] The present invention is related to memory ownership, and more particularly to determining memory ownership based on cache lines to detect self-correcting code. Background technique [0002] Self-modified code (self modified code, SMC) has at least one instruction executed by a local processor to modify another instruction, or a sequence of program codes subsequently processed by the processor. The self-modifying program code may have a sequence of program codes to modify the program code that was just executed, so that the program code that was modified to have a new function is executed again. In another example, self-modifying code is used to modify immediately preceding code that is executed. Although self-modifying code is not as common today as it used to be, many legacy programs still have self-modifying code and should be implemented properly. Processors must be able to detect self-correcting code and correct operations to avoid inappropriate...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/30047G06F9/30189
Inventor 布兰特·比恩柯林·艾迪
Owner VIA ALLIANCE SEMICON CO LTD