AXI protocol-based DMA controller and data uploading method

Abstract

The invention discloses an AXI protocol-based DMA controller and a data uploading method. The AXI protocol-based DMA controller comprises a channel module, an arbitration module, a control module, a data cache module, an interruption module and a configuration interface module, wherein the channel module is used for providing an information transmission channel for the whole controller; the arbitration module is used for arbitrating information in the channel, selecting passable transmission commands and sending the passable transmission commands to the control module; the control module is used for processing a received read-write command, converting the read-write command into a read-write signal according with an AXI protocol, and transmitting the read-write signal out; the data cache module is used for receiving to-be-uploaded data from the control module and the transmission command from the channel module; the interruption module is used for receiving the signal from the control module and sending an information transmission state to the exterior; and the configuration interface module is an interface for configuring parameters of registers in the modules. Compared with the prior art, the AXI protocol-based DMA controller and the data uploading method have the effects of realizing the high-speed data transfer between peripheral equipment and a memory, and improving the working efficiency of the whole system.

Description

technical field [0001] The invention relates to the technical field of computer application, in particular to a highly practical AXI protocol-based DMA controller and a data uploading method. Background technique [0002] In SOC design, with the continuous improvement of CPU processing capability, improving the bandwidth of the bus and the work efficiency of each device has become the key to improving system performance. Due to the high performance of the AXI bus itself and the wide application of ARM microprocessors, AXI has become a widely used bus standard in SOC design. A high-performance bus must have a compatible peripheral device interface in order to construct a system-on-chip with complete functions. Every time ARM Company introduces a new bus standard, it will provide IPs of various peripheral interfaces one after another, but these IPs are often expensive. So in order to better meet the specific project needs, while saving costs and reducing the project budget, ...

AI Technical Summary

Problems solved by technology

Every time ARM introduces a new bus standard, it will successively provide IPs for various peripheral interfaces, but these IPs are often expensive

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