Co-processor IP core of programmable convolutional neural network

A technology of convolutional neural network and coprocessor, which is applied in the design field of programmable convolutional neural network coprocessor IP core, can solve the problems of long time consumption and high cost, achieve the advantage of energy consumption ratio and reduce chip power consumption Compared with energy consumption, the effect is obvious

Active Publication Date: 2017-07-11
XI AN JIAOTONG UNIV
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AI Technical Summary

Problems solved by technology

As we all know, direct modification and debugging of hardware design is a costly and time-consuming process

Method used

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  • Co-processor IP core of programmable convolutional neural network
  • Co-processor IP core of programmable convolutional neural network
  • Co-processor IP core of programmable convolutional neural network

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Experimental program
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Embodiment Construction

[0044] Firstly, the following basic definition of convolution operation is given for the following specific implementation description:

[0045] -fi: Input feature, which is the input matrix of the convolutional layer. Here is an analysis of the general situation, assuming that the two-dimensional input feature is a square, and the three dimensions are defined as (is, is, ci), which respectively represent the length, width and number of channels of the input feature.

[0046] -fo: Output feature, that is, the output matrix after the calculation of the convolutional layer. The three dimensions are (os, os, co), which respectively represent the length, width and number of channels of the output feature.

[0047] -w: weight matrix, that is, convolution kernel. Here it is assumed that the convolution kernel is a square, and the four dimensions are (k, k, ci, co), where ci corresponds to the input feature, and co corresponds to the variable definition of the same name of the outpu...

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Abstract

The present invention discloses a co-processor IP core of a programmable convolutional neural network. The invention aims to realize the arithmetic acceleration of the convolutional neural network on a digital chip (FPGA or ASIC). The co-processor IP core specifically comprises a global controller, an I / O controller, a multi-level cache system, a convolution unit, a pooling unit, a filling unit, a full-connection unit, an internal interconnection logical unit, and an instruction set designed for the co-processor IP. The proposed hardware structure supports the complete flows of convolutional neural networks diversified in scale. The hardware-level parallelism is fully utilized and the multi-level cache system is designed. As a result, the characteristics of high performance, low power consumption and the like are realized. The operation flow is controlled through instructions, so that the programmability and the configurability are realized. The co-processor IP core can be easily applied to different application scenes.

Description

technical field [0001] The invention relates to the field of digital chip design, in particular to the design of a programmable convolutional neural network coprocessor IP core. Background technique [0002] The exploration, research and realization of artificial intelligence (AI) has always been the tireless pursuit of human beings. As one of the most important branches of computer science, artificial intelligence science originated in the middle of the 20th century with the birth of computer science, and gradually developed into an interdisciplinary science in many fields such as computer, mathematics, electronics, biology, medicine and engineering. [0003] Machine learning (Machine Learning) is currently the most core and fastest-growing branch in the field of artificial intelligence. It is dedicated to the study of automatic analysis and acquisition of laws from data through certain learning algorithms, and then predicts unknown data by models. Machine learning theory ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/045
Inventor 梁峰高震霆杨少飞买廷瑞
Owner XI AN JIAOTONG UNIV
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