Coarse-grained reconfigurable convolution neural network accelerator and system

Abstract

The invention provides a coarse-grained reconfigurable convolution neural network accelerator and a system. The accelerator comprises a number of processing unit clusters. Each processing unit cluster comprises a number of basic computing units which are connected through a sub-addition unit. The sub-addition units of a number of processing unit clusters are respectively connected with a mother addition unit. Each sub addition unit is used for generating partial sum of a number of adjacent basic computing units. The mother addition unit is used for accumulating the sub-addition units. According to the invention, a coarse-grained reconfigurable way is adopted to link different weights and image tracks through SRAM or other interconnection units to realize different convolution kernel processing structures; the accelerator can effectively support networks and convolution cores of different sizes; and the cost of reconfiguration is significantly reduced.

Description

technical field [0001] The invention relates to the technical field of high-energy-efficiency hardware accelerator design, and more particularly, to a coarse-grained reconfigurable convolutional neural network accelerator and system. Background technique [0002] Convolutional Neural Network (CNN) is a feedforward neural network. Its artificial neurons can respond to surrounding units within a part of the coverage area, and it has excellent performance for large-scale image processing. Convolutional neural networks have become the most commonly used algorithms in the fields of image recognition and speech recognition. This type of method requires a lot of calculations and requires the design of dedicated accelerators. It also has good application prospects in mobile devices. However, due to the limited resources of mobile devices, accelerators currently designed on GPU and FPGA (Field Programmable Gate Array, Field Programmable Gate Array) platforms are difficult to use on ...

AI Technical Summary

Problems solved by technology

Traditional DSP (Digital Signal Processing, digital signal processing) has the disadvantages of low computing speed, non-reconfigurable hardware structure, long development and upgrading cycle and non-portability. This shortcoming is more obvious when facing large-scale computing.

ASIC has great advantages in terms of performance, area, and power consumption, but the changing application requirements and rapidly increasing complexity make ASIC design and verification difficult, and the development cycle is long, making it difficult to meet the requirements of rapid product application.

In programmable logic devices, although Xilinx's Virtex-6 series FPGA uses a 600MHz DSP48E1slice to achieve a performance of more than 1000GMACS (1×1012 multiplication and accumulation operations / second), but for large-scale calculations, the circuit that needs to be configured The scale is too large, the synthesis and configuration time is too long, and the actual operating frequency is not high, it is difficult to maintain high performance while pursuing the goal of flexibility and low power consumption

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