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Topology circuit of three-level DCDC current transformer and common-mode voltage restraining method

A topology circuit and converter technology, applied in the direction of adjusting electrical variables, converting DC power input to DC power output, instruments, etc., can solve the problems of low common mode voltage and high common mode voltage of three-level DCDC circuit

Active Publication Date: 2017-08-22
SHENZHEN SINEXCEL ELECTRIC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The embodiment of the present application solves the technical problem of high common-mode voltage of the three-level DCDC circuit in the prior art by providing a topology circuit and a common-mode voltage suppression method of the three-level DCDC converter, and realizes the control of the three-level DCDC converter. Suppression of the common mode voltage on the DC side of the flat DCDC circuit, so that the common mode voltage is lower than the power conversion voltage

Method used

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  • Topology circuit of three-level DCDC current transformer and common-mode voltage restraining method
  • Topology circuit of three-level DCDC current transformer and common-mode voltage restraining method
  • Topology circuit of three-level DCDC current transformer and common-mode voltage restraining method

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Embodiment 1

[0052] Please refer to figure 2 , the embodiment of the present application provides a topology circuit of a three-level DCDC converter, the topology circuit includes: a DC source U batt21 , the first to the eighth capacitor unit, the first inductance unit L 21 , the second inductance unit L 22 and the first to fourth transistors (Q 21 ~Q 24 ); wherein, each transistor is provided with a parasitic diode between the drain and the source, which are respectively diodes (D 21 ~D 24 );

[0053] The first capacitor unit includes a first capacitor C 21 , whose two ends are directly connected to the DC source U batt21 Positive and negative port connections;

[0054] The first transistor Q 21 The first end passes through the first inductance unit L 21 with the DC source U batt21 connected to the positive port, the first transistor Q 21 The second end of the second end is grounded through the second capacitor unit; the second capacitor unit includes a second capacitor C 22...

Embodiment 2

[0080] Based on the same inventive concept, the embodiment of the present application also provides a common-mode voltage suppression method for a three-level DCDC converter, which is applied to the topology circuit described in Embodiment 1. Please refer to figure 2 , the topological circuit includes a first connection point a, a second connection point N and a third connection point b, and the first transistor Q 21 with the second transistor Q 22 Connected through the first connection point a, the second transistor Q 22 with the third transistor Q 23 Connected through the second connection point N, the third transistor Q 23 with the fourth transistor Q 24 Connected through the third connection point b; the common mode voltage suppression method includes:

[0081] at DC source U batt21 The connection between the positive port and the second connection point N includes an eleventh capacitor C 211 The ninth capacitor unit, and the DC source U batt21 The connection betwe...

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Abstract

The invention discloses a topology circuit of a three-level DCDC current transformer and a common-mode voltage restraining method. The objective of the invention is to solve a technical problem of high common-mode voltage of a three-level DCDC current transformer. The topology circuit comprises a direct current (Ubatt21), first to twelfth capacitors (C21-C212), a first inductor unit (L21), a second inductor unit (L22) and first to fourth transistor units (Q21-Q24). By providing a novel topology structure, capacitance larger than stray capacitance is added in the middle of a connection line where a connection point N of the second transistor (Q22) and the third transistor (Q23) at the positive and negative ports of the direct current source (Ubatt21). Thus, a technical problem of the high common-mode voltage of a three-level DCDC current transformer in the prior art is effectively solved; restraining on the high common-mode voltage of the three-level DCDC current transformer is achieved; and the common-mode voltage is lower than electric energy conversion voltage.

Description

technical field [0001] The invention relates to a DCDC converter, in particular to a topology circuit and a common-mode voltage suppression method of a three-level DCDC converter. Background technique [0002] DCDC converter (Direct Current-Direct Current Converter), that is, DC to DC (conversion between different DC power values), can be called a DCDC converter as long as it meets this definition. [0003] The DCDC circuit realizes the change between high and low voltage direct current, and can adapt to a wider range of input and output voltages; the three-level technology is applied to high voltage and high power DCDC circuits, such as figure 1 As shown, it is a topological circuit where a three-level DCDC circuit is applied to a bipolar DCAC converter, including: a three-level DCDC circuit and a DCAC conversion circuit, wherein the three-level DCDC circuit includes: a DC source U batt11 , capacitance (C 11 ~C 13 ), inductance L 11 , four insulated gate bipolar transis...

Claims

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Application Information

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IPC IPC(8): H02M3/158H02M1/12
CPCH02M1/12H02M3/1584H02M1/123Y02B70/10
Inventor 刘立刚范小波
Owner SHENZHEN SINEXCEL ELECTRIC
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