LLR-BP decoder adaptive to code lengths

Abstract

The invention discloses an LLR-BP decoder adaptive to code lengths. The LLR-BP decoder comprises an initial data buffer module, a check node processing module, an intermediate information storage module, a variable node processing module, a control module, an output cache module, and decoding determining module. In the Xilinx ISE14.7 environment, a partially parallel LDPC decoder structure is designed which uses an early termination iterative decoding strategy to reduce the number of iteration times of an algorithm. By using a limit taking method, the operation of a complex probability function in the LLR-BP decoding algorithm is implemented, thereby reducing the implementation complexity of the algorithm. On the premise of ensuring a bit error rate, the decoder improves decoding speed, reduces a hardware logic resource occupancy rate, and solves simultaneous decoding of multiple code lengths.

Description

technical field [0001] The invention belongs to the technical field of channel coding, in particular to an adaptive code length LLR-BP decoder. Background technique [0002] LDPC code is Low Density Parity Check Code (Low Density Parity Check Code), a class of linear block codes with sparse parity check matrix proposed by Dr. Robert G. Gallager in 1962. Not only has good performance close to the Shannon limit, but also has low decoding complexity and flexible structure. It is still a research hotspot in the field of channel coding in recent years and has a good application prospect in mobile communications. [0003] With the increase of the code length, the dimension of the LDPC decoding matrix increases greatly, the complexity of the algorithm increases greatly, and the hardware logic resources for decoding are occupied more. In-depth research has been carried out on soft and hard decision algorithms and FPGA implementation, mainly including the following algorithms. [0...

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