Double diffused drain NMOS device and manufacturing method

Abstract

The invention discloses a double diffused drain NMOS device. An N-type buried layer is on a P-type substrate, and an N-type epitaxial layer is on the N-type buried layer; the N-type epitaxial layer has a P well and a drift region, a channel region of the double diffused drain NMOS device is between the P well and the drift region, and a silicon surface on the channel region is a gate oxide layer and a polysilicon grid electrode of the double diffused drain NMOS device; the P well has a doped P-type region and a source region of the double diffused drain NMOS device, and the drift region has a drain region of the double diffused drain NMOS device; the P well and the drift region respectively have a P-type doped layer which is respectively under the source region and the drain region; exhaust of the drift region is facilitated by the P-type doped layer, and a breakdown voltage is improved; the P-type doped layer under the source region has small influence on the device, and a threshold voltage almost has no change; drift region concentration of a current path does not decrease, no rise of conduction resistance of the device is guaranteed. The double diffused drain NMOS device is advantaged in that the breakdown voltage is improved without adding a mask, and cost does not increase.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a double-diffusion drain NMOS device, and also relates to a manufacturing method of the double-diffusion drain NMOS device. Background technique [0002] DDD MOS (Double Diffused Drain MOSFET) high-voltage double-diffused drain devices are widely used in circuit output interfaces, LCD drive circuits, etc., and their operating voltage is about 10-20V. DDD MOS is easily compatible with the traditional CMOS process, the process is simpler than LD MOS, and the manufacturing cost is lower. [0003] Breakdown voltage is particularly important as a key parameter to measure DDD MOS devices. [0004] The structure of the original double diffused drain NMOS device is as follows figure 1 As shown, on the P-type substrate 1 is an N-type buried layer 2 , and on it is an N-type epitaxial layer 3 . The drift region 4 and the P-well 5 are located in the epitaxy 3 . The drift region concentratio...

AI Technical Summary

Problems solved by technology

Usually the drift region cannot be completely depleted resulting in a lower breakdown voltage, but if the breakdown voltage is increased by reducing the concentration of the drift region, the on-resistance will increase

Therefore, usually the two cannot be taken into account, and only a trade-off can be made to obtain a more balanced value.

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