memory access unit
A technology of memory access and memory, which is applied in the field of memory access unit, and can solve the problems of increasing computing overhead and storage requirements
Active Publication Date: 2020-11-17
RENESAS ELECTRONICS EURO
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However, this increases computational overhead as well as storage requirements
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[0072] In the following description, unless otherwise specified, all constants, variables, and registers are integer types.
[0073] memory system 1
[0074] figure 1 is a schematic block diagram of a memory system 1 useful for understanding the present invention.
[0075] refer to figure 1 , the memory system 1 includes n random access memory (RAM) modules 2 1 ,…,2 n Memory 2 in the form of an array (wherein n is an integer greater than 1). memory module 2 1 ,…,2 n Can take the form of memory macros. The memory system 1 also includes bus connections 3 and memory access circuitry 4 interconnecting the memory 2 with a bus 5 consisting of an address bus 6 and a data bus 7 .
[0076] The memory access circuit 4 includes an address calculator 8 (also called “address decoder”), a data multiplexer 9 , and a bus interface 10 .
[0077] 2 per memory module 1 ,…,2 n Has memory data width w_m. In this example, the memory data width w_m is 128 bits. In this example, the data...
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A memory access unit (24; 74 1 ,...,74 m ), for processing samples of d-dimensional arrays in one of m data buses (27; 77) and k*m memories (22 1 ,…,twenty two k ;72 1 ,...,72 k*m ), where m≥1, k≥2. The memory access unit includes k address calculators (28 1 ,...,28 k ;79 1 ,...,79 k ), each address calculator is configured to receive a bus address (A_B), add a corresponding offset to generate a sample bus address (A_B'), and to access a sample, generate from said sample bus address according to the addressing scheme The corresponding address (A_1, . . . , A_d) in each of the d dimensions is accessed along one of the dimensions according to the bus address according to the addressing scheme. The memory access unit includes k sample collectors (29 1 ,...,29 k ;80 1 ,...,80 k*m ), each sample collector is operable to generate a memory select (CS) with respect to one of the k*m memories so that between a predetermined location in the bus data word and a corresponding one of the k*m memories transfer samples. Each sample collector (29 1 ,...,29 k ;80 1 ,...,80 k*m ) is configured to calculate the corresponding memory selection according to the addresses in each of the d dimensions, so that the sample collector selects a different one of the k*m memories, thereby allowing the sample collector to access k*m concurrently k memories out of m memories. The memory controller may include m data buses (77 1 ,...,77 m ) and k*m memories (72 1 ,...,72 k*m m memory access units (74 1 ,...,74 m ).
Description
technical field [0001] The present invention relates to a memory access unit and to a memory controller comprising one or more memory access units. Background technique [0002] Motor vehicles are increasingly being equipped with different forms of sensors for detecting harmful conditions. These sensors generate large amounts of data in multiple dimensions. Ideally, samples should be stored sequentially in memory to allow hardware accelerators to process them efficiently. However, it is often necessary to process samples in more than one dimension. [0003] One solution is to reorder samples between processing steps. However, this increases computational overhead as well as storage requirements. [0004] Another approach is to use memory that allows data to be read out in orthogonal dimensions. An example of such a memory is described in WO2009 / 003115A1. Contents of the invention [0005] The present invention seeks to provide a memory access unit for handling transf...
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IPC IPC(8): G06F12/02G06F12/06G06F13/16G01S13/28G01S13/524G01S13/87G01S13/931
CPCG01S13/28G01S13/5246G01S13/87G06F12/0207G06F12/0607G06F13/1647G01S13/931G06F2212/1016G01S13/53
Inventor 马西亚斯·格吕内瓦尔德
Owner RENESAS ELECTRONICS EURO