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High-speed custom floating point divider of complex numbers

A floating-point complex number and self-defined technology, which is applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve the problem of consuming large resources, achieve overall performance enhancement, fast calculation, balance algorithm accuracy and resource consumption Effect

Active Publication Date: 2017-09-05
湖南兰茜生物科技有限公司
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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a custom floating Implementation method of point complex divider

Method used

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  • High-speed custom floating point divider of complex numbers
  • High-speed custom floating point divider of complex numbers
  • High-speed custom floating point divider of complex numbers

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Embodiment Construction

[0040] The following uses a specific example of a 64-bit custom floating-point format complex number divider to illustrate the implementation of the present invention, wherein the bit width of the exponent part is 12, and the bit width of the mantissa part is 52. figure 1 It is an overall flowchart of the present invention, and the whole flow process can be divided into three major steps:

[0041] In the first step, implement A, B, and C using a custom floating-point multiply-accumulate unit:

[0042] figure 2 It is an illustration of A=a×c+b×d. a=Man(a)×2 Exp(a) ,b=Man(b)×2 Exp(b) ,c=Man(c)×2 Exp(c) ,d=Man(d)×2 Exp(d) .

[0043] After multiplying the mantissa, the high bit of the obtained product is intercepted to 52 bits, and the obtained result and the exponent part are used as the input of the basic adder at the same time, that is, the bit width of the mantissa part of the basic adder is 52, and the bit width of the exponent part for 12. Then perform high-order in...

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Abstract

The invention provides a design method of a high-speed custom floating point divider of complex numbers based on FPGA (field programmable gate array). According to its basic principle, division of complex numbers is converted into division of real numbers, and real and imaginary parts are subjected concurrently to division operation by means of dependency of divisor-reciprocal iteration process in multiplication iteration so as to obtain a real part and imaginary part of a quotient. According to the technical scheme, first, real and imagery parts of a divisor and dividend are calculated through a custom floating point multiplying unit and an adding unit; second, division of the real and imaginary parts is performed concurrently; third, standard formatted output is provided. By taking advantage of high-speed line structure of the FPGA, the high-speed custom floating point divider of complex numbers has the advantages that high precision is met, resources are saved greatly, and operation speed is increased.

Description

technical field [0001] The invention relates to the field of high-speed real-time digital signal processing, in particular to a method for realizing a divider, in particular to the realization of a high-speed self-defined floating-point complex divider. Background technique [0002] In the fields of scientific computing, digital signal processing, especially communication digital signal processing, floating-point division is one of the important operations. Compared with other addition (subtraction) and multiplication operations, the design of the division operation is more complicated, and it takes more time to calculate the quotient. Therefore, for those applications with high-speed real-time requirements, a high-performance floating-point divider is very important. [0003] There are three main categories of classic division algorithms: look-up table method (LUT), digital recursion algorithm (Digital Recurrence) and function iteration algorithm (Functional Iteration). Am...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/487
CPCG06F7/4873
Inventor 余莉韩方剑黄少冰
Owner 湖南兰茜生物科技有限公司
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