A High Speed ​​Programmable Arbitrary Integer Frequency Divider

Abstract

The invention discloses a high-speed programmable arbitrary integer frequency divider, and relates to the field of high-speed programmable multi-mode frequency dividers in microelectronic technology. The structure consists of fixed divider DIV 1 , fixed divider DIV 2 , programmable divider DIV 3 , and the realization of the programmable counter Counter. DIV 1 、DIV 2 、DIV 3 The frequency dividers are based on the shift register, driven by the input clock, belong to the synchronous frequency division, can work at a higher frequency, and have a smaller phase noise contribution. Divider DIV 1 for fixed M 1 frequency divider; frequency divider DIV 2 for fixed M 2 frequency divider; frequency divider DIV 3 Programmable 1~M 3 Frequency division; Counter Counter is a programmable 1-N counter. Aiming at the fact that the traditional programmable multi-mode integer frequency divider cannot work at a higher frequency and an arbitrary integer frequency division range at the same time, the present invention proposes a structure of a high-speed programmable arbitrary integer frequency divider based on a shift register, which is suitable for high-speed, wide-band range of multimode frequency division applications.

Description

technical field [0001] The invention relates to the field of high-speed programmable multi-mode frequency dividers in microelectronic technology, in particular to the field of high-speed programmable frequency dividers for arbitrary integer frequency division. Background technique [0002] Programmable frequency divider, usually used in frequency synthesizer, divides the output frequency and the reference frequency into the phase frequency detector (PFD) for comparison. In a phase-locked loop (PLL), the main function of the programmable frequency divider is to reduce the operating frequency of the PFD and change the output frequency of the PLL. With the development of integrated circuits and the speed requirements of the system, the output frequency of the PLL is getting higher and higher, requiring the programmable frequency divider to work at a higher frequency, which is a difficult point in the design of the PLL. Some traditional programmable frequency dividers , can rea...

AI Technical Summary

Problems solved by technology

With the development of integrated circuits and the speed requirements of the system, the output frequency of the PLL is getting higher and higher, requiring the programmable frequency divider to work at a higher frequency, which is a difficult point in the design of the PLL. Some traditional programmable frequency dividers , can realize arbitrary integer frequency division, but the working speed is slow; dual-mode prescaler can realize high-speed frequency division, and is often used in the case of continuous frequency division with relatively large frequency division, and cannot achieve arbitrary integer frequency division; asynchronous division Frequency structure, due to inter-stage delay, high-speed frequency division cannot be achieved

In the article "A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved" published on IEEE in July 2013, a design of a high-speed arbitrary integer frequency divider is disclosed. However, due to the circuit structure, different OR gate and asynchronous frequency division make the output waveform seriously distorted and have large phase noise, which limits its application range

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