Timing error estimation method based on leader sequence
A technology of timing error and preamble sequence, applied in digital transmission systems, electrical components, synchronization devices, etc., can solve the problem that timing error estimation cannot represent timing synchronization adjustment step range, timing error normalization offset, etc. Fast convergence, simplified algorithm implementation, and reduced time overhead
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[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
[0021] Such as figure 1 As shown, the flow process of a timing error estimation method based on the preamble sequence in this embodiment is as follows: (1) matching decimation filter
[0022] The input digital signal after ADC sampling, the sampling rate is f sample ,(f sample = 2 N f symbol , f symbol is the signal symbol rate, N is a natural number), the input digital signal is reduced by the matched decimation filter (i.e. the sliding correlation signal sampling rate f corr ). Wherein the decimation factor of the matched decimation filter is defined as M=N-1, then N>M, and N≥3. In order to simplify the amount of resources required for the Fourier butterfly transform, it is assumed that there are 2 sampling points in a signal symbol after matching extraction, that is, N=M+1.
[0023] (2) Preamble sequence sliding correlator
[002...
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