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Polarity searching method of fixed-polarity Reed-Muller logic circuit

A technology of logic circuit and search method, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems that the search process cannot be carried out effectively, the diversity of the population is reduced, and the convergence speed is slow, so as to achieve enhanced local optimum And the ability to avoid premature, ensure global convergence, and avoid the effect of destruction

Active Publication Date: 2017-11-07
BEIHANG UNIV
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  • Claims
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AI Technical Summary

Problems solved by technology

[0004] (1) The selection operation of the genetic algorithm itself makes the variance and entropy of the population evolve in the direction of decreasing, thereby reducing the diversity of the population;
[0005] (2) The genetic algorithm is essentially a random search optimization algorithm. When the problem scale is large or the problem is more complex, the search space will increase sharply.
In addition, group dispersion and convergence contradict each other, resulting in slower convergence speed;
[0006] (3) When the fitness of individuals in the population is not much different, the new individuals in the offspring population are also similar, making the search process ineffective, and the selection mechanism based on fitness tends to be purely random selection, thus falling into local best
However, traditional differential evolution algorithms are mainly used to solve global optimization problems with continuous variables, and cannot solve discrete binary coded combinatorial optimization problems like FPRM logic circuit polarity search.

Method used

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  • Polarity searching method of fixed-polarity Reed-Muller logic circuit
  • Polarity searching method of fixed-polarity Reed-Muller logic circuit
  • Polarity searching method of fixed-polarity Reed-Muller logic circuit

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Embodiment Construction

[0031] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0032] figure 1 It is a flow chart of a polarity search method for an FPRM logic circuit of the present invention. Such as figure 1 As shown, the method includes:

[0033] Step 1, read the Boolean logic circuit;

[0034] Step 2, input evolution parameters;

[0035] Step 3, randomly generate an initial population, where polarity is encoded as a binary individual;

[0036] Further, among them, the individual initialization operation can be expressed as:

[0037]

[0038] x i,j表 represents the j-th element of the i-th individual, and rand represents a random number between 0 and 1.

[0039] Step 4, perform an improved binary random mutation operation;

[0040] Further, among them, the improved binary random mutation operation can be expressed as:

[0041]

[0042] v i,j Denotes th...

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Abstract

The invention provides a polarity searching method of a fixed-polarity Reed-Muller logic circuit. The best polarity of an FPRM logic circuit is searched by using the new binary differential evolution algorithm, compared with a polarity searching method of the FPRM logic circuit based on the genetic algorithm, the capacity of local optimum and the capacity of premature convergence are avoided, and the convergence rate and the polarity searching efficiency are improved. The method comprises the following steps that firstly, a Boolean logic circuit is read; secondly, an evolution parameter is input; thirdly, an initial population is generated randomly, wherein the polarity is encoded into a binary individual; fourthly, the improved binary stochastic mutation operation is performed; fifthly, the binomial crossover operation is performed; an FPRM expression of the target individual and the FPRM expression of a test individual of the target individual are obtained; seventhly, the fitness value of the target individual and the fitness value of the test individual of the target individual are calculated; eighthly, the greedy selection operation and an elitism selection strategy are performed; ninthly, if the current evolution algebra is smaller than the maximum evolution algebra, the fourth to eighth steps are executed in sequence, and otherwise, the best polarity is output.

Description

technical field [0001] The invention relates to the field of polarity optimization of Reed-Muller logic circuits, in particular to a polarity search method for fixed-polarity Reed-Muller logic circuits based on a new binary differential evolution algorithm. Background technique [0002] Logic circuits can be represented by Boolean logic based on AND / OR / NOT operations, or Reed-Muller (RM) logic based on AND / XOR or OR / XNOR operations. For circuits such as arithmetic circuits, parity check circuits, and communication circuits, RM logic representation has greater advantages in terms of power consumption, area, and speed than Boolean logic representation. Fixed Polarity RM (Fixed Polarity RM, FPRM) expression is a more popular standard RM expression. For a logistic function of n variables, it has 2 n FPRM expressions of different polarities. The polarity directly determines the complexity of the FPRM expression, which in turn affects the performance of the circuit. Therefore,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/327
Inventor 肖利民何振学李明哲霍志胜
Owner BEIHANG UNIV
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