A Three-Word Line Memory Cell Based on Finfet Device

Abstract

The present invention discloses a three-word line memory cell based on a FinFET device. The three word line memory cell comprises a bit line, a write bit line, a write word line, a read / write word line, an inverted read / write word line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET , a fifth FinFET, and a sixth FinFET. The first FinFET and the second FinFET are separately a low threshold P-type FinFET; the third FinFET is a high-threshold N-type FinFET; and the fourth FinFET, the fifth FinFET, and the sixth FinFET are separately a low-threshold N-type FinFET. Advantages of the three-word line memory cell disclosed by the present invention are that: the delay, power consumption, and power consumption delay products are relatively small without affecting the performance of the circuit, data values stored in the storage point cannot be destroyed during the read operation, the storage result is stable and the circuit function is stable.

Description

technical field [0001] The invention relates to a storage unit, in particular to a three-word line storage unit based on a FinFET device. Background technique [0002] As the process size enters the nanometer level, power consumption has become a problem that IC designers have to pay attention to. In most digital systems, memory power consumption accounts for an increasing proportion of total circuit power consumption. Static Random Access Memory (SRAM, Static Random Access Memory) is an important component in memory, so it is of great research significance to design SRAM with high stability and low power consumption. The SRAM is mainly composed of a storage array and other peripheral circuits, and the storage array is composed of a storage unit, which is the core of the SRAM, and the performance of the storage unit directly determines the performance of the SRAM. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and the current m...

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Problems solved by technology

The storage unit may destroy the data value stored in the storage point during the read operation, thus causing unstable storage results and unstable circuit functions; moreover, the pull-down network formed by the FINFET tube M3 and the FINFET tube M4 has a certain value when the storage unit is in the holding state. There are two leakage current paths, so the leakage current is large, resulting in large leakage power consumption and large delay, which is not conducive to fast and stable data access

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