Method, device and system for multiple processors to share memory access

A processor and memory technology, applied in the computer field, can solve problems such as the inability to set up a single memory, the inability to arrange multiple processors and memories, and the reduction of system processing capacity, so as to achieve the effect of improving system processing capacity

Active Publication Date: 2020-05-05
北京金石智信科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Due to the limitation of the board area, it is impossible to set up a memory (NorFlash) for each processor on the board
In the prior art, it is impossible to arrange multiple processors and memories in the limited space of a single board without changing the area of ​​the single board.
The current common practice is to reduce the number of processors and memory settings on a single board. Although this can ensure the normal operation of the entire system, it will also bring about a significant reduction in system processing capacity.

Method used

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  • Method, device and system for multiple processors to share memory access
  • Method, device and system for multiple processors to share memory access
  • Method, device and system for multiple processors to share memory access

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Embodiment Construction

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted.

[0053] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in ...

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PUM

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Abstract

The invention discloses a method capable of shared access of multiple processors to a memory, wherein controllers used to control mutual communication connection are disposed between the multiple processors and the memory. The method comprises the steps that a storage space of the memory is divided into multiple storage sub-spaces; according to the quantity of the processors and an address space of the storage space of the memory, access addresses are distributed to each storage sub-space; the controllers map output addresses of the processors to access addresses of the storage sub-spaces; and the controllers control the processors to access the corresponding storage sub-spaces one after another according to mapping relations between the output addresses of the processors and the access addresses of the storage sub-spaces. According to the invention, the function of letting the multiple processors access the storage at different time and in different spaces is achieved; problems such as poor system processing capacity caused by PCB area limiting and other similar reasons can be solved; and system processing capacity can be enhanced on the premise that the single board area is not changed.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a method, device and system for sharing memory access by multiple processors. Background technique [0002] In single-board systems that use NorFlash memory as the storage medium for system boot firmware, the more conventional implementation is that each processor (CPU) is connected to a single external memory (NorFlash), and because the external address / data bus of the processor (CPU) Most of them are time-division multiplexing access methods, so a latch chip must be added between the processor (CPU) and the memory (NorFlash). [0003] Due to the limitation of the area of ​​the single board, it is impossible to set up a memory (NorFlash) for each processor on the single board. In the prior art, on the premise of not changing the area of ​​the single board, it is still impossible to arrange multiple processors and memories in the limited space of the single board. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/167
CPCG06F15/167
Inventor 郑亚银
Owner 北京金石智信科技有限公司
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